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1. 发明申请

US20090187799A1 Common test logic for multiple operation modes 失效
标题翻译：多种操作模式的通用测试逻辑
公开(公告)号：US20090187799A1
公开(公告)日：2009-07-23
申请号：US12010000
申请日：2008-01-23
申请人： Talal Jaber , David M. Wu , Ming Zhang
发明人： Talal Jaber , David M. Wu , Ming Zhang
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547 , G01R31/31858 , G06F11/2236
摘要： In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn, each MISR may includes bit cells, each having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first and second cells. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个逻辑单元以对数据执行操作的处理器。每个单元可以在逻辑单元的输入处包括多输入移位寄存器（MISR），以将数据从输入信号收集和压缩到单元。反过来，每个MISR可以包括位单元，每个位单元具有接收输入数据并由第一时钟信号控制的第一单元，第二单元接收第一单元的输出并由第二时钟信号控制;掩模单元，接收所述第二单元的输出并且响应于屏蔽时钟信号产生屏蔽信号，以及耦合在所述第一和第二单元之间的多路复用器。描述和要求保护其他实施例。

2. 发明授权

US07734972B2 Common test logic for multiple operation modes 失效
标题翻译：多种操作模式的通用测试逻辑
公开(公告)号：US07734972B2
公开(公告)日：2010-06-08
申请号：US12010000
申请日：2008-01-23
申请人： Talal Jaber , David M. Wu , Ming Zhang
发明人： Talal Jaber , David M. Wu , Ming Zhang
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/31858 , G06F11/2236
摘要： In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn, each MISR may includes bit cells, each having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first and second cells. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个逻辑单元以对数据执行操作的处理器。每个单元可以在逻辑单元的输入处包括多输入移位寄存器（MISR），以将数据从输入信号收集和压缩到单元。反过来，每个MISR可以包括位单元，每个位单元具有接收输入数据并由第一时钟信号控制的第一单元，第二单元接收第一单元的输出并由第二时钟信号控制;掩模单元，接收所述第二单元的输出并且响应于屏蔽时钟信号产生屏蔽信号，以及耦合在所述第一和第二单元之间的多路复用器。描述和要求保护其他实施例。

3. 发明申请

US20070168767A1 Flexible scan architecture 审中-公开
公开(公告)号：US20070168767A1
公开(公告)日：2007-07-19
申请号：US11520203
申请日：2006-09-12
申请人： Talal Jaber , Srinivas Patil , Larry Thatcher , Chih-Jen Lin , Anil Sabbavarapu , David Wu , Madhukar Reddy
发明人： Talal Jaber , Srinivas Patil , Larry Thatcher , Chih-Jen Lin , Anil Sabbavarapu , David Wu , Madhukar Reddy
IPC分类号： G11B20/20 , G06K5/04 , G11B5/00
CPC分类号： G01R31/318552 , G01R31/318594 , G06F11/2236
摘要： A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

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