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1. 发明申请

US20050215026A1 Method for producing semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20050215026A1
公开(公告)日：2005-09-29
申请号：US11087585
申请日：2005-03-24
申请人： Takuo Ohashi , Taishi Kubota , Susumu Sakurai , Takayuki Kanda
发明人： Takuo Ohashi , Taishi Kubota , Susumu Sakurai , Takayuki Kanda
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76224 , H01L21/823481
摘要： With respect to nitriding of an oxide film on an inner wall of a trench, a method for producing a semiconductor device is provided, the method preventing the characteristic deterioration of the semiconductor device by controlling and optimizing peak nitrogen concentration in an oxide film to reduce the stress and to suppress the threshold voltage shift due to the positive charge of nitrogen.
摘要翻译：关于在沟槽的内壁上的氧化膜的氮化，提供了一种半导体器件的制造方法，该方法通过控制和优化氧化物膜中的氮浓度来降低半导体器件的特性劣化，从而减少应力并抑制由氮的正电荷引起的阈值电压偏移。

2. 发明申请

US20050227452A1 Method for producing semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20050227452A1
公开(公告)日：2005-10-13
申请号：US11103613
申请日：2005-04-12
申请人： Takuo Ohashi , Takeshi Suwa , Taishi Kubota
发明人： Takuo Ohashi , Takeshi Suwa , Taishi Kubota
IPC分类号： H01L21/76 , H01L21/28 , H01L21/316 , H01L21/324 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76224 , H01L21/28185 , H01L21/28238
摘要： A method for producing a semiconductor device includes the steps of forming a trench for device isolation on a silicon substrate; and annealing the silicon substrate in an atmosphere containing a noble gas at any step after the growth of a buried oxide film until the growth of a gate polysilicon.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在硅衬底上形成用于器件隔离的沟槽; 并且在掩埋氧化膜生长之后的任何步骤，在含有惰性气体的气氛中退火硅衬底直到栅极多晶硅的生长。

3. 发明授权

US07592234B2 Method for forming a nitrogen-containing gate insulating film 失效
标题翻译：形成含氮栅极绝缘膜的方法
公开(公告)号：US07592234B2
公开(公告)日：2009-09-22
申请号：US11833894
申请日：2007-08-03
申请人： Takuo Ohashi , Taishi Kubota
发明人： Takuo Ohashi , Taishi Kubota
IPC分类号： H01L21/76
CPC分类号： H01L21/3141 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/0228 , H01L21/02304 , H01L21/02332 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L21/31612 , H01L21/3185 , H01L29/518
摘要： A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitride layer by using an atomic layer deposition process, to obtain a gate insulating film having a higher nitrogen concentration, while suppressing the nitrogen concentration in the vicinity of the gate insulating film and the silicon substrate.
摘要翻译：形成含氮栅极绝缘膜的方法包括以下步骤：在硅衬底上形成氧化硅膜，对氧化硅膜的顶部进行氮化以形成氮化硅薄层，并在其上形成氮化硅膜通过使用原子层沉积工艺获得具有较高氮浓度的栅极绝缘膜，同时抑制栅极绝缘膜和硅衬底附近的氮浓度。

4. 发明申请

US20070099364A1 Method for manufacturing a semiconductor device having a polymetal gate electrode 审中-公开
标题翻译：一种具有多金属栅电极的半导体器件的制造方法
公开(公告)号：US20070099364A1
公开(公告)日：2007-05-03
申请号：US11586493
申请日：2006-10-26
申请人： Takuo Ohashi , Taishi Kubota , Toru Miyazaki , Shigetomi Michimata , Satoru Yamada
发明人： Takuo Ohashi , Taishi Kubota , Toru Miyazaki , Shigetomi Michimata , Satoru Yamada
IPC分类号： H01L21/8234 , H01L21/8242 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/10873 , H01L21/28061 , H01L21/28247 , H01L21/823828 , H01L21/823857
摘要： A method for forming a semiconductor device having a polymetal gate electrode includes the steps of forming a gate oxide film on a silicon substrate, forming a polysilicon film and a tungsten film on the gate oxide film, patterning the polysilicon film and tungsten film, and thermally oxidizing the polysilicon film in an oxidizing atmosphere including water and hydrogen at a substrate-surface temperature of 850 degrees C. and a water content of 7% to 20%.
摘要翻译：一种形成具有多金属栅电极的半导体器件的方法包括以下步骤：在硅衬底上形成栅极氧化膜，在栅极氧化膜上形成多晶硅膜和钨膜，对多晶硅膜和钨膜进行构图，在850℃的基板表面温度和7％〜20％的含水量下，在包括水和氢的氧化气氛中氧化多晶硅膜。

5. 发明授权

US07163871B2 Manufacturing method of semiconductor device and oxidization method of semiconductor substrate 有权
标题翻译：半导体器件的制造方法和半导体衬底的氧化方法
公开(公告)号：US07163871B2
公开(公告)日：2007-01-16
申请号：US10763244
申请日：2004-01-26
申请人： Taishi Kubota , Yoshihiro Kitamura , Takuo Ohashi , Susumu Sakurai , Takayuki Kanda , Shinichi Horibe
发明人： Taishi Kubota , Yoshihiro Kitamura , Takuo Ohashi , Susumu Sakurai , Takayuki Kanda , Shinichi Horibe
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A manufacturing method of a semiconductor device having a trench is provided to form, at a corner portion of the trench, an oxide film which is greater in thickness and smaller in stress than at other portions. When the trench formed in the semiconductor substrate is oxidized, it is oxidized in an oxygen environment containing dichloroethylene at a predetermined weight percent to allow the formation of an oxide film having a greater thickness at the corner portion of the trench than thickness at other portions, whereby the semiconductor device improving dielectric breakdown characteristics can be obtained.
摘要翻译：提供具有沟槽的半导体器件的制造方法，以在沟槽的角部形成厚度大于应力的氧化膜，其压力小于其它部分。当在半导体衬底中形成的沟槽被氧化时，其在含有二氯乙烯的氧环境中以预定的重量百分数被氧化，以允许在沟槽的角部比其它部分的厚度形成厚度更大的氧化膜，从而可以获得提高绝缘击穿特性的半导体器件。

6. 发明申请

US20060166459A1 Semiconductor apparatus and method of producing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060166459A1
公开(公告)日：2006-07-27
申请号：US11338728
申请日：2006-01-25
申请人： Takuo Ohashi , Takeshi Suwa , Susumu Sakurai , Taishi Kubota
发明人： Takuo Ohashi , Takeshi Suwa , Susumu Sakurai , Taishi Kubota
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/76224 , H01L21/823481
摘要： In a method of producing a semiconductor apparatus, which method includes a trench forming step of forming a trench in a silicon substrate and an inner wall oxidizing step of forming an oxide film on an inner wall of the trench; the inner wall oxidizing step being performed by wet oxidization with a low concentration of moisture mixed in oxygen to form the oxide film so that a stress caused between the oxide film and the silicon substrate is not greater than 3.5×109 (dyne/cm2) and a radius at a corner of the trench is 8 nm or more.
摘要翻译：在制造半导体装置的方法中，该方法包括在硅衬底中形成沟槽的沟槽形成步骤和在沟槽的内壁上形成氧化膜的内壁氧化步骤; 内壁氧化步骤通过在氧气中混合的低浓度的湿气进行湿式氧化来形成氧化膜，使得在氧化膜和硅衬底之间产生的应力不大于3.5×10 9 >（达因/厘米2），沟槽角部的半径为8nm以上。

7. 发明授权

US5065215A Semiconductor memory cell and method of manufacturing the same 失效
标题翻译：半导体存储单元及其制造方法
公开(公告)号：US5065215A
公开(公告)日：1991-11-12
申请号：US542427
申请日：1990-06-22
申请人： Taishi Kubota
发明人： Taishi Kubota
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10835
摘要： A semiconductor memory includes a plurality of semiconductor memory cells formed in a matrix form on a semiconductor substrate, each semiconductor memory cell having a memory cell including a trench capacitor, a bit line, and a word line extending perpendicularly to the bit line. The word lines of semiconductor memory cells adjacent in a direction of the bit lines substantially vertically overlap each other. A method of manufacturing the above semiconductor memory includes the steps of forming a first word line of a given semiconductor memory cell, and forming a second word line of a semiconductor memory cell adjacent to the given semiconductor memory cell in a direction of the bit line on the first word line, so that the second word line overlaps the first word line in a substantially insulated state.
摘要翻译：半导体存储器包括在半导体衬底上以矩阵形式形成的多个半导体存储单元，每个半导体存储单元具有包括沟槽电容器，位线和垂直于位线延伸的字线的存储单元。在位线的方向上相邻的半导体存储单元的字线基本上垂直地彼此重叠。一种制造上述半导体存储器的方法包括以下步骤：形成给定半导体存储单元的第一字线，以及在位线方向上形成与给定半导体存储单元相邻的半导体存储单元的第二字线第一字线，使得第二字线在基本绝缘状态下与第一字线重叠。

8. 发明授权

US5973355A Nonvolatile semiconductor memory device and manufacturing method of the same 失效
标题翻译：非易失性半导体存储器件及其制造方法相同
公开(公告)号：US5973355A
公开(公告)日：1999-10-26
申请号：US851285
申请日：1997-05-05
申请人： Hiroki Shirai , Taishi Kubota , Ichiro Honma , Hirohito Watanabe , Haruhiko Ono , Takeshi Okazawa
发明人： Hiroki Shirai , Taishi Kubota , Ichiro Honma , Hirohito Watanabe , Haruhiko Ono , Takeshi Okazawa
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7883 , Y10S257/90
摘要： There is disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.
摘要翻译：公开了一种非易失性半导体存储器件，即使在不增加制造步骤的数量的情况下，即使在微细尺寸形成存储单元时，也能够保持高电容比。在具有掩埋扩散层型电池的闪速存储器中，源极区域和漏极区域形成为与其上表面具有突出和凹陷部分的多晶硅膜的多晶膜图案自对准地形成。

9. 发明授权

US5757044A Electrically erasable and programmable read only memory cell with split floating gate for preventing cell from over-erase 失效
标题翻译：电可擦除可编程只读存储单元，具有分离浮动栅极，可防止电池过度擦除
公开(公告)号：US5757044A
公开(公告)日：1998-05-26
申请号：US548523
申请日：1995-10-26
申请人： Taishi Kubota
发明人： Taishi Kubota
IPC分类号： H01L21/8247 , G11C11/56 , G11C16/04 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/4232 , G11C11/5621 , G11C16/0458 , H01L29/7887 , G11C2211/5612
摘要： A floating gate type field effect transistor has a plurality of floating gate sub-electrodes on a lower gate oxide layer electrically isolated from one another; even if one of the floating gate sub-electrodes changes a part of a channel region thereunder to depletion state due to an over-erase, the over-erase does not affect the function of the floating gate type field effect transistor, because another sub-electrode transfers and cuts off channel current depending upon the amount of electrons accumulated therein.
摘要翻译：浮栅型场效应晶体管在彼此电隔离的下栅极氧化物层上具有多个浮置栅极子电极; 即使其中一个浮置栅极子电极由于过度擦除将其中的沟道区域的一部分改变为耗尽状态，因此，过擦除不会影响浮置栅极型场效应晶体管的功能，电极根据其中积累的电子的量转移并切断通道电流。

10. 发明授权

US06300185B1 Polyacrystalline silicon film formation method 有权
标题翻译：多晶硅薄膜的形成方法
公开(公告)号：US06300185B1
公开(公告)日：2001-10-09
申请号：US09345344
申请日：1999-07-01
申请人： Taishi Kubota
发明人： Taishi Kubota
IPC分类号： H01L218234
CPC分类号： H01L21/28035 , C23C16/24 , H01L21/32055
摘要： In a method of forming a polycrystalline silicon film, the polycrystalline silicon film is formed under film formation conditions of a film formation rate of 0.9rav to 1.1rav, where rav (nm/minute) is an average rate of forming the polycrystalline silicon film on each of a plurality of substrates on which oxide films are formed so as to provide the roughness of the interface between the oxide film on the substrate and the polycrystalline silicon film of less than 1 nm. As a result, it is possible to decrease the roughness of the interface between a gate oxide film and the polycrystalline silicon film and to improve reliability for ensuring the long-time use of the gate oxide film.
摘要翻译：在形成多晶硅膜的方法中，在成膜速度为0.9rav至1.1rav的成膜条件下形成多晶硅膜，其中rav（nm /分钟）是形成多晶硅膜的平均速率在其上形成氧化膜的多个基板中的每一个，以便提供基板上的氧化物膜和多晶硅膜之间的界面的粗糙度小于1nm。结果，可以降低栅极氧化膜和多晶硅膜之间的界面的粗糙度，并且提高确保长期使用栅极氧化膜的可靠性。

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