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1. 发明申请

US20120012807A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120012807A1
公开(公告)日：2012-01-19
申请号：US13182095
申请日：2011-07-13
申请人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
发明人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2409 , H01L45/08 , H01L45/1233
摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
摘要翻译：实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。可变电阻层由过渡金属氧化物构成。构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。

2. 发明授权

US08759806B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08759806B2
公开(公告)日：2014-06-24
申请号：US13182095
申请日：2011-07-13
申请人： Takeshi Yamaguchi , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
发明人： Takeshi Yamaguchi , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
IPC分类号： H01L29/02
CPC分类号： H01L45/146 , H01L27/2409 , H01L45/08 , H01L45/1233
摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
摘要翻译：实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。可变电阻层由过渡金属氧化物构成。构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。

3. 发明申请

US20110103128A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110103128A1
公开(公告)日：2011-05-05
申请号：US12882685
申请日：2010-09-15
申请人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
发明人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译：一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

4. 发明授权

US08320158B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08320158B2
公开(公告)日：2012-11-27
申请号：US12882685
申请日：2010-09-15
申请人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
发明人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译：一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

5. 发明授权

US08391048B2 Non-volatile semiconductor memory device including memory cells with a variable resistor 有权
标题翻译：包括具有可变电阻器的存储单元的非易失性半导体存储器件
公开(公告)号：US08391048B2
公开(公告)日：2013-03-05
申请号：US12846198
申请日：2010-07-29
申请人： Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
发明人： Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
摘要翻译：根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给选择的存储单元。擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

6. 发明申请

US20090263950A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090263950A1
公开(公告)日：2009-10-22
申请号：US12491984
申请日：2009-06-25
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×10 20 cm -3或更高至1×10 22 cm -3或更小的铝原子。

7. 发明授权

US07964489B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07964489B2
公开(公告)日：2011-06-21
申请号：US12491984
申请日：2009-06-25
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L21/3205
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×1020cm-3或更高至1×1022cm-3或更低的铝原子。

8. 发明授权

US07807990B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07807990B2
公开(公告)日：2010-10-05
申请号：US11753186
申请日：2007-05-24
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L31/00
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×1020cm-3或更高至1×1022cm-3或更低的铝原子。

9. 发明申请

US20080128822A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080128822A1
公开(公告)日：2008-06-05
申请号：US11753186
申请日：2007-05-24
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×10 20 cm -3或更多至1×10 22 cm -3的铝原子， 3 以下。

10. 发明授权

US08988925B2 Nonvolatile semiconductor memory device in which polarities of voltages in forming operation and set operation are different from each other 有权
标题翻译：非易失性半导体存储器件，其中成形操作和设定操作中的电压的极性彼此不同
公开(公告)号：US08988925B2
公开(公告)日：2015-03-24
申请号：US13597318
申请日：2012-08-29
申请人： Reika Ichihara , Takayuki Tsukamoto
发明人： Reika Ichihara , Takayuki Tsukamoto
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C11/00 , G11C2013/0083
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。多个第二线延伸以与第一线相交。多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。控制电路被配置为控制施加到存储器单元的电压。控制电路在成形操作期间向可变电阻器施加第一脉冲电压。此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。

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