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1. 发明申请

US20050055698A1 Server-driven data synchronization method and system 审中-公开
标题翻译：服务器驱动的数据同步方法和系统
公开(公告)号：US20050055698A1
公开(公告)日：2005-03-10
申请号：US10658269
申请日：2003-09-10
申请人： Takeshi Sasaki , Masato Inoue , Akio Kita
发明人： Takeshi Sasaki , Masato Inoue , Akio Kita
IPC分类号： H04L12/28 , H04L12/56 , H04L29/06 , H04L29/08 , G06F15/16
CPC分类号： H04L67/1095 , H04L29/06 , H04L69/329 , H04W56/00 , H04W68/00 , H04W74/06 , H04W99/00
摘要： A method and system for synchronizing data between a network server and a mobile device is provided. An object instance may be replicated in response to a replication request received from the network server, and a notification message may be created. The notification message may be sent to the mobile device in response to a polling request received from the mobile device, and the replicated object instance may be sent to the mobile device in response to a synchronization request received from the mobile device.
摘要翻译：提供了一种用于在网络服务器和移动设备之间同步数据的方法和系统。可以响应于从网络服务器接收到的复制请求来复制对象实例，并且可以创建通知消息。可以响应于从移动设备接收到的轮询请求将通知消息发送到移动设备，并且可以响应于从移动设备接收的同步请求将复制对象实例发送到移动设备。

2. 发明申请

US20080072674A1 Ultrasound systems and method for measuring weld penetration depth in real time and off line 有权
标题翻译：用于实时和离线测量焊缝穿透深度的超声系统和方法
公开(公告)号：US20080072674A1
公开(公告)日：2008-03-27
申请号：US11895217
申请日：2007-08-23
申请人： Ifeanyi Ume , Akio Kita
发明人： Ifeanyi Ume , Akio Kita
IPC分类号： G01N29/34
CPC分类号： G01N29/0618 , G01N29/2412 , G01N29/2418 , G01N2291/02854 , G01N2291/0422 , G01N2291/0423 , G01N2291/0426 , G01N2291/0428 , G01N2291/267
摘要： Disclosed are systems and methods that permit both real-time, and off-line, measurement of weld penetration depth. Exemplary systems and methods comprise an ultrasound source, such as a pulsed Nd:Yag laser, that simultaneously generates longitudinal and shear waves that radiate adjacent one side of a weld joining two specimens. An ultrasonic sensor, such as an electro-magnetic acoustic transducer or a piezo-electric transducer, capable of detecting shear and/or longitudinal waves, is disposed on an opposite side of the weld from the source. A signal processor is coupled to the sensor that processes time of flight signals for selected longitudinal or shear waves transmitted across the weld seam. The signal processor implements an algorithm that computes the weld penetration depth from the time of flight signals.
摘要翻译：公开了允许焊接穿透深度的实时和离线测量的系统和方法。示例性系统和方法包括超声源，例如脉冲Nd：Yag激光器，其同时产生辐射邻近连接两个样本的焊缝的一侧的纵波和剪切波。诸如电磁换能器或压电换能器的能够检测剪切和/或纵波的超声波传感器设置在与源的焊接的相对侧上。信号处理器耦合到传感器，其处理跨过焊缝传输的所选纵向或剪切波的飞行时间信号。信号处理器实现了从飞行时间信号计算焊接穿透深度的算法。

3. 发明授权

US4873557A MIS FET and process of fabricating the same 失效
标题翻译： MIS FET及其制造工艺
公开(公告)号：US4873557A
公开(公告)日：1989-10-10
申请号：US67413
申请日：1987-06-19
申请人： Akio Kita
发明人： Akio Kita
IPC分类号： H01L21/336 , H01L29/45 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/456 , H01L29/78 , H01L29/665 , Y10S257/90
摘要： An LDD MIS FET comprises a silicide over the lightly doped regions to reduce the parasitic resistance and to prevent the depletion of the lightly-doped regions, reducing the hot carrier injection effect. By the provision of the silicide, the overall parasitic resistance can be made low. Moreover, the increase in the resistance of the lightly-doped region due to the negative charge being trapped at the interface of or in the oxide film over the lighty-doped region and the resultant degradation in the characteristic are eliminated.
摘要翻译： LDD MIS FET包括在轻掺杂区域上的硅化物以减少寄生电阻并防止轻掺杂区域的耗尽，减少热载流子注入效应。通过提供硅化物，可以使整体寄生电阻较低。此外，由于负电荷被捕获在光掺杂区域上的氧化物膜的界面处或在氧化膜上的轻掺杂区域的电阻的增加以及由此导致的特性降低。

4. 发明申请

US20130092447A1 Downhole Tool Impact Dissipating Tool 有权
标题翻译：井下工具冲击耗散工具
公开(公告)号：US20130092447A1
公开(公告)日：2013-04-18
申请号：US13276076
申请日：2011-10-18
申请人： Alan J. Sallwasser , Bulent Finci , Jaime Pedraza , Akio Kita
发明人： Alan J. Sallwasser , Bulent Finci , Jaime Pedraza , Akio Kita
IPC分类号： E21B17/00
CPC分类号： E21B17/07
摘要： An impact dissipation tool for supporting a downhole tool in downhole applications. The tool includes a base and a housing. The tool also includes a carriage located within the housing and coupled to the base, the carriage being movable relative to the housing upon a predetermined impact force. A dissipator disposed inside the housing is collapsible due to the relative movement of the carriage and the housing. The collapse of the dissipator dissipates the impact force transferred to the downhole tool.
摘要翻译：用于在井下应用中支撑井下工具的冲击耗散工具。该工具包括底座和外壳。工具还包括位于壳体内并联接到基座的滑架，滑架可在预定的冲击力下相对于壳体移动。由于托架和壳体的相对移动，设置在壳体内部的耗散器可折叠。耗散器的塌陷消散了传递到井下工具的冲击力。

5. 发明授权

US07762136B2 Ultrasound systems and method for measuring weld penetration depth in real time and off line 有权
标题翻译：用于实时和离线测量焊缝穿透深度的超声系统和方法
公开(公告)号：US07762136B2
公开(公告)日：2010-07-27
申请号：US11895217
申请日：2007-08-23
申请人： Ifeanyi C. Ume , Akio Kita
发明人： Ifeanyi C. Ume , Akio Kita
IPC分类号： G01N29/07
CPC分类号： G01N29/0618 , G01N29/2412 , G01N29/2418 , G01N2291/02854 , G01N2291/0422 , G01N2291/0423 , G01N2291/0426 , G01N2291/0428 , G01N2291/267
摘要： Disclosed are systems and methods that permit both real-time, and off-line, measurement of weld penetration depth. Exemplary systems and methods comprise an ultrasound source, such as a pulsed Nd:Yag laser, that simultaneously generates longitudinal and shear waves that radiate adjacent one side of a weld joining two specimens. An ultrasonic sensor, such as an electro-magnetic acoustic transducer or a piezo-electric transducer, capable of detecting shear and/or longitudinal waves, is disposed on an opposite side of the weld from the source. A signal processor is coupled to the sensor that processes time of flight signals for selected longitudinal or shear waves transmitted across the weld seam. The signal processor implements an algorithm that computes the weld penetration depth from the time of flight signals.
摘要翻译：公开了允许焊接穿透深度的实时和离线测量的系统和方法。示例性系统和方法包括超声源，例如脉冲Nd：Yag激光器，其同时产生辐射邻近连接两个样本的焊缝的一侧的纵波和剪切波。诸如电磁换能器或压电换能器的能够检测剪切和/或纵波的超声波传感器设置在与源的焊接的相对侧上。信号处理器耦合到传感器，其处理跨过焊缝传输的所选纵向或剪切波的飞行时间信号。信号处理器实现了从飞行时间信号计算焊接穿透深度的算法。

6. 发明授权

US09217328B2 Automated sidewall coring 有权
标题翻译：自动侧壁取芯
公开(公告)号：US09217328B2
公开(公告)日：2015-12-22
申请号：US13500538
申请日：2010-10-08
申请人： Bo Yang , Steve E. Buchanan , Akio Kita
发明人： Bo Yang , Steve E. Buchanan , Akio Kita
IPC分类号： E21B49/06 , E21B44/02 , E21B44/04 , E21B44/00
CPC分类号： E21B49/06 , E21B44/005 , E21B44/02 , E21B44/04
摘要： Methods and apparatus for positioning a downhole tool in a wellbore extending into a subterranean formation, commencing coring operations by rotating a coring bit of the downhole tool and extending the rotating coring bit into a sidewall of the wellbore, sensing a parameter associated with the coring operations, and adjusting the coring operations based on the sensed parameter.
摘要翻译：用于将井下工具定位在延伸到地下地层中的井眼中的方法和装置，通过旋转井下工具的取芯钻头并将旋转的取芯钻头延伸到井眼的侧壁中来开始取芯操作，感测与取芯操作相关的参数并且基于所感测的参数来调整取芯操作。

7. 发明申请

US20120318579A1 Automated Sidewall Coring 有权
标题翻译：自动侧壁取芯
公开(公告)号：US20120318579A1
公开(公告)日：2012-12-20
申请号：US13500538
申请日：2010-10-08
申请人： Bo Yang , Steve E. Buchanan , Akio Kita
发明人： Bo Yang , Steve E. Buchanan , Akio Kita
IPC分类号： E21B25/16
CPC分类号： E21B49/06 , E21B44/005 , E21B44/02 , E21B44/04
摘要： Methods and apparatus for positioning a downhole tool in a wellbore extending into a subterranean formation, commencing coring operations by rotating a coring bit of the downhole tool and extending the rotating coring bit into a sidewall of the wellbore, sensing a parameter associated with the coring operations, and adjusting the coring operations based on the sensed parameter.
摘要翻译：用于将井下工具定位在延伸到地下地层中的井眼中的方法和装置，通过旋转井下工具的取芯钻头并将旋转的取芯钻头延伸到井眼的侧壁中来开始取芯操作，感测与取芯操作相关的参数并且基于所感测的参数来调整取芯操作。

8. 发明授权

US5618745A Method of manufacturing a one transistor one-capacitor memory cell structure with a trench containing a conductor penetrating a buried insulating film 失效
标题翻译：制造具有包含穿透掩埋绝缘膜的导体的沟槽的一个晶体管单电容器存储单元结构的方法
公开(公告)号：US5618745A
公开(公告)日：1997-04-08
申请号：US366505
申请日：1994-12-30
申请人： Akio Kita
发明人： Akio Kita
IPC分类号： H01L27/04 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/78 , H01L29/786 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10861 , H01L21/76251 , H01L27/10829 , H01L27/1203
摘要： A method of manufacturing a one-transistor one-capacitor memory cell structure. In a first step, a buried insulating film layer is formed in a semiconductor substrate and a semiconductor layer is formed on the buried insulating film layer. In a second step, a capacitor trench is formed in the substrate by penetrating through the buried layer and a dielectric film layer is formed on an inner side wall surface of the trench. Then, a conductive material is filled into the trench to form a capacitor. Finally, an MIS transistor is formed in the semiconductor layer adjacent to the trench capacitor such that either the drain or the source makes contact with the conductive material.
摘要翻译：一种制造单晶体管单电容器存储单元结构的方法。在第一步骤中，在半导体衬底中形成掩埋绝缘膜层，并在掩埋绝缘膜层上形成半导体层。在第二步骤中，通过穿过掩埋层在衬底中形成电容器沟槽，并且在沟槽的内侧壁表面上形成电介质膜层。然后，将导电材料填充到沟槽中以形成电容器。最后，在与沟槽电容器相邻的半导体层中形成MIS晶体管，使得漏极或源极与导电材料接触。

9. 发明授权

US4948744A Process of fabricating a MISFET 失效
标题翻译：制造MISFET的工艺
公开(公告)号：US4948744A
公开(公告)日：1990-08-14
申请号：US430972
申请日：1989-11-01
申请人： Akio Kita
发明人： Akio Kita
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , Y10S148/106 , Y10S148/118 , Y10S257/90
摘要： In a process of fabricating a MISFET of the LDD structure, a gate insulation film is formed on a semiconductor substrate or a semiconductor thin film. A gate electrode is formed on the gate insulation film, and lightly-doped regions are formed in the semiconductor substrate or the semiconductor thin film by ion implantation using the gate electrode as a mask. Next, a CVD oxide film containing an impurity is unselectively deposited, sidewalls are formed along the edges of the gate electrodes by anisotropic etching, and heavily-doped source and drain regions are formed in the semiconductor substrate or the semiconductor thin film by ion implanation using the gate electrode and the sidewalls as a mask.
摘要翻译：在制造LDD结构的MISFET的过程中，在半导体衬底或半导体薄膜上形成栅极绝缘膜。栅电极形成在栅极绝缘膜上，并且通过使用栅电极作为掩模的离子注入在半导体衬底或半导体薄膜中形成轻掺杂区域。接下来，非选择性地沉积含有杂质的CVD氧化膜，通过各向异性蚀刻沿着栅电极的边缘形成侧壁，并且通过离子注入在半导体衬底或半导体薄膜中形成重掺杂的源极和漏极区域，使用栅电极和侧壁作为掩模。

10. 发明申请

US20140279586A1 INVOICE NUMBER GAP ALERTING AND PROCESSING 审中-公开
标题翻译：发票号码报警和处理
公开(公告)号：US20140279586A1
公开(公告)日：2014-09-18
申请号：US13797425
申请日：2013-03-12
申请人： Akio Kita
发明人： Akio Kita
IPC分类号： G06Q10/10 , G06Q50/18
CPC分类号： G06Q10/10 , G06Q40/12
摘要： Various embodiments illustrated and described herein include at least one of systems, methods, and software for invoice gap number alerting and processing. Some such embodiments include monitoring, within a computing system involved in at least one of invoice generation and storing, continuity of invoice numbering. Upon noting a missing invoice number, some embodiments include stopping creation of invoices and pushing an alert to a managing entity responsive to noting the missing invoice number. Input will typically be received from the managing entity regarding a missing invoice number. In response to the received input, various embodiments further facilitate registration of the missing invoice number to enable creation of the new invoice and restart creation of invoices.
摘要翻译：本文所示和描述的各种实施例包括用于发票差距号警报和处理的系统，方法和软件中的至少一个。一些这样的实施例包括在涉及发票生成和存储中的至少一个的计算系统内监视发票编号的连续性。在注意到缺少的发票号码时，一些实施例包括停止创建发票并且响应于注意到丢失的发票号码向管理实体推送警报。通常从管理实体收到有关缺少发票编号的输入。响应于所接收的输入，各种实施例进一步便于登记缺失的发票号码，以便能够创建新的发票并重新开始发票。

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