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1. 发明授权

US5485034A Semiconductor device including bipolar transistor having shallowed base 失效
标题翻译：包括具有浅基极的双极晶体管的半导体器件
公开(公告)号：US5485034A
公开(公告)日：1996-01-16
申请号：US344694
申请日：1994-11-18
申请人： Takeo Maeda , Hiroshi Gojohbori , Yoshitaka Tsunashima
发明人： Takeo Maeda , Hiroshi Gojohbori , Yoshitaka Tsunashima
IPC分类号： H01L29/73 , H01L21/331 , H01L27/06 , H01L29/10 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7322 , H01L27/0623 , H01L29/1004
摘要： A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.
摘要翻译：本发明的半导体器件包括用作双极晶体管的集电极的N型半导体区域，掺杂有硼并与N型半导体区域的表面接触形成的二氧化硅膜，P型半导体区域形成为与N型半导体区域中掺杂有硼的二氧化硅膜接触并用作双极晶体管的基极，并且形成在P型半导体区域中并用作发光体的N型半导体区域双极晶体管。

2. 发明授权

US5406115A Semiconductor device including bipolar transistor having shallowed base and method for manufacturing the same 失效
标题翻译：包括具有浅基底的双极晶体管的半导体器件及其制造方法
公开(公告)号：US5406115A
公开(公告)日：1995-04-11
申请号：US52919
申请日：1993-04-27
申请人： Takeo Maeda , Hiroshi Gojohbori , Yoshitaka Tsunashima
发明人： Takeo Maeda , Hiroshi Gojohbori , Yoshitaka Tsunashima
IPC分类号： H01L29/73 , H01L21/331 , H01L27/06 , H01L29/10 , H01L29/732 , H01L29/72 , H01L27/02
CPC分类号： H01L29/7322 , H01L27/0623 , H01L29/1004
摘要： A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.
摘要翻译：本发明的半导体器件包括用作双极晶体管的集电极的N型半导体区域，掺杂有硼并与N型半导体区域的表面接触形成的二氧化硅膜，P型半导体区域形成为与N型半导体区域中掺杂有硼的二氧化硅膜接触并用作双极晶体管的基极，并且形成在P型半导体区域中并用作发光体的N型半导体区域双极晶体管。

3. 发明授权

US5442226A Bipolar transistor having an emitter electrode formed of polysilicon 失效
标题翻译：具有由多晶硅形成的发射极的双极晶体管
公开(公告)号：US5442226A
公开(公告)日：1995-08-15
申请号：US51780
申请日：1993-04-26
申请人： Takeo Maeda , Hiroshi Gojohbori , Takeo Nakayama
发明人： Takeo Maeda , Hiroshi Gojohbori , Takeo Nakayama
IPC分类号： H01L21/8249 , H01L27/06 , H01L29/417 , H01L29/735 , H01L29/43
CPC分类号： H01L27/0623 , H01L29/41708
摘要： In a semiconductor device, an emitter electrode has a polysilicon layer provided in a first contact hole and on a first insulating film. The polysilicon layer is in contact with an emitter region and is covered with a metal layer. A second contact hole is provided on a part of a second insulating film located on a substantially flat portion of the metal layer. A third contact hole is provided in those portions of the first insulating film and a second insulating layer which are located on a base region.
摘要翻译：在半导体器件中，发射极电极具有设置在第一接触孔中的第一绝缘膜上的多晶硅层。多晶硅层与发射极区域接触并被金属层覆盖。第二接触孔设置在位于金属层的基本平坦部分上的第二绝缘膜的一部分上。第三接触孔设置在位于基底区域的第一绝缘膜和第二绝缘层的那些部分中。

4. 发明授权

US5576572A Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5576572A
公开(公告)日：1996-11-19
申请号：US235214
申请日：1994-04-29
申请人： Takeo Maeda , Hiroshi Gojohbori
发明人： Takeo Maeda , Hiroshi Gojohbori
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/102 , H01L29/417 , H01L29/76
CPC分类号： H01L27/0623 , H01L29/41708
摘要： A semiconductor integrated circuit device having a bipolar transistor and contact in the form of a wired layer by using different impurities for doping the emitter electrode and the wired layer of the device, both of which are made of polysilicon. The emitter electrode, formed on an emitter region of a p-type silicon semiconductor substrate, is doped with an n-type impurity having a low diffusion coefficient. A polysilicon wired layer, formed on an impurity diffusion region in an active region of the semiconductor substrate, is doped with another impurity that can effectively destroy native oxide films. With such an arrangement of selectively using impurities, the temperature of thermally treating the emitter region can be less than 850.degree. C.
摘要翻译：一种半导体集成电路器件，其具有双极性晶体管，并且通过使用不同的杂质来接触布线层，所述杂质掺杂了由多晶硅制成的发射极和器件的布线层。在p型硅半导体衬底的发射极区域上形成的发射极被掺杂有低扩散系数的n型杂质。在半导体衬底的有源区域中的杂质扩散区上形成的多晶硅布线层掺杂有可以有效地破坏天然氧化物膜的另一种杂质。通过选择性地使用杂质的这种布置，热处理发射极区域的温度可以低于850℃。

5. 发明授权

US5578518A Method of manufacturing a trench isolation having round corners 失效
标题翻译：制造具有圆角的沟槽隔离件的方法
公开(公告)号：US5578518A
公开(公告)日：1996-11-26
申请号：US356526
申请日：1994-12-15
申请人： Hidetoshi Koike , Kazunari Ishimaru , Hiroshi Gojohbori , Fumitomo Matsuoka
发明人： Hidetoshi Koike , Kazunari Ishimaru , Hiroshi Gojohbori , Fumitomo Matsuoka
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/762 , Y10S148/05 , Y10S148/161 , Y10S438/911
摘要： A semiconductor device comprises a semiconductor substrate having a major surface, a trench device isolation region having a trench selectively formed to define at least one island region in the major surface of the semiconductor substrate and a filler insulatively formed within the trench, an elongated gate electrode insulatively formed over a central portion of the island region so that each of its both ends which are opposed to each other in the direction of its length overlaps the trench device isolation region, and source and drain regions formed within the island region on the both sides of the gate electrode. The surface of the trench device isolation region is formed lower than the major surface of the semiconductor substrate. Those portions of the major surface of the semiconductor substrate that are located under the gate electrode at the boundary with the trench device isolation region are rounded, and the radius of curvature of these portions of the major surface of the semiconductor substrate is selected to be not less than 50 nm.
摘要翻译：一种半导体器件包括具有主表面的半导体衬底，沟槽器件隔离区，其具有选择性地形成以限定半导体衬底的主表面中的至少一个岛区和在沟槽内绝缘地形成的填料的沟槽;细长栅电极绝缘地形成在岛状区域的中心部分上，使得其长度方向上彼此相对的两端各自与沟槽器件隔离区域重叠，并且形成在两侧的岛区域内的源极和漏极区域的栅电极。沟槽器件隔离区域的表面形成为低于半导体衬底的主表面。半导体衬底的与沟槽器件隔离区的边界位于栅极下方的主表面的那些部分是圆形的，并且半导体衬底的主表面的这些部分的曲率半径被选择为不小于50nm。

6. 发明授权

US5733801A Method of making a semiconductor device with alignment marks 失效
标题翻译：制造具有对准标记的半导体器件的方法
公开(公告)号：US5733801A
公开(公告)日：1998-03-31
申请号：US674210
申请日：1996-07-01
申请人： Hiroshi Gojohbori
发明人： Hiroshi Gojohbori
IPC分类号： H01L21/76 , H01L21/02 , H01L21/027 , H01L21/311 , H01L21/465 , H01L23/544
CPC分类号： H01L21/31111 , H01L21/465 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002
摘要： A first trench is formed in an element-separating region on the surface of a semiconductor substrate, and a second trench is formed in an alignment mark region thereof. When a first insulating substance is deposited on the substrate surface so as to bury the first and second trenches, a first insulating film is formed into a recessed shape in both the first and second trenches. A second insulating substance having an etching rate slower than that of the first insulating substance is formed on the first insulating film, and further etched to leave the second insulating film only over the second trench. The overall thickness of the device is reduced in such a way that the upper surface of the first insulating film in the first trench becomes flush with the semiconductor substrate surface. A part of the surface of the insulating substance on the alignment mark portion projects so as to be usable as an alignment mark. Alternatively, when a first trench is formed extending to both the element-separating and alignment mark regions and further when an insulating film is deposited on the substrate surface so as to bury both the first and second trenches, a first projecting insulating film can be formed between the two trenches. A second insulating film whose etching rate is slower than that of the first insulating film is formed on the projecting insulating film and further etched to leave the second insulating film so as to cover only the first projecting insulating film. The overall thickness is reduced in such a way that the upper surface of the first insulating film becomes flush with the semiconductor substrate surface, and further the remaining second insulating film is removed. The remaining first insulating film is usable as an alignment mark portion.
摘要翻译：第一沟槽形成在半导体衬底的表面上的元件分离区域中，并且第二沟槽形成在其对准标记区域中。当第一绝缘物质沉积在衬底表面上以便掩埋第一和第二沟槽时，第一绝缘膜在第一和第二沟槽都形成为凹形。在第一绝缘膜上形成具有比第一绝缘物质慢的蚀刻速率的第二绝缘物质，并进一步蚀刻以仅在第二沟槽上留下第二绝缘膜。器件的整体厚度减小，使得第一沟槽中的第一绝缘膜的上表面与半导体衬底表面齐平。对准标记部分上的绝缘物质的表面的一部分突出以便可用作对准标记。或者，当形成延伸到元件分离和对准标记区域的第一沟槽时，并且当绝缘膜沉积在衬底表面上以便掩埋第一和第二沟槽两者时，可以形成第一突出的绝缘膜两条沟之间。在突出绝缘膜上形成蚀刻速度慢于第一绝缘膜的第二绝缘膜，并进一步蚀刻以留下第二绝缘膜，以仅覆盖第一突出绝缘膜。整体厚度减小，使得第一绝缘膜的上表面与半导体衬底表面齐平，并且还剩余的第二绝缘膜被去除。剩余的第一绝缘膜可用作对准标记部分。

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