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1. 发明授权

US4813408A Engine cooling device 失效
标题翻译：发动机冷却装置
公开(公告)号：US4813408A
公开(公告)日：1989-03-21
申请号：US33994
申请日：1987-04-01
申请人： Takehiko Katsumoto , Yoshiaki Danno , Daisuke Sanbayashi , Takashi Dogahara , Hidetsugu Kanao , Katsuo Akishino , Osamu Hirako , Hiroshi Kamada , Taizou Kitada , Masahiko Matsuda , Nobuaki Shimizu , Masaji Asada , Yoshinari Fukami , Takaaki Hirano
发明人： Takehiko Katsumoto , Yoshiaki Danno , Daisuke Sanbayashi , Takashi Dogahara , Hidetsugu Kanao , Katsuo Akishino , Osamu Hirako , Hiroshi Kamada , Taizou Kitada , Masahiko Matsuda , Nobuaki Shimizu , Masaji Asada , Yoshinari Fukami , Takaaki Hirano
IPC分类号： F01L1/053 , F01M1/16 , F01P3/00 , F01P3/02 , F01P9/00 , F02F1/16 , F02F7/00 , F01M1/00
CPC分类号： F01P3/02 , F01L1/0532 , F01M1/16 , F01P9/00 , F02F1/16 , F01P2003/006 , F02B2275/18 , F02F7/006
摘要： An engine cooling device comprises an oil jacket surrounding a cylinder portion of an engine, an oil gallery supplying high-pressure oil to various parts of the engine, and an oil pressure regulator disposed between the oil jacket and the oil gallery to reduce the pressure of the high-pressure oil supplied from the oil gallery and to supply the oil at a reduced pressure to the oil jacket. Thus, the required mechanical strength of the oil jacket can be decreased to decrease the weight of the engine cylinder block.
摘要翻译：发动机冷却装置包括围绕发动机的气缸部分的油套，向发动机的各个部分供应高压油的油道和设置在油套和油库之间的油压调节器，以减小从油田供应的高压油，并将油减压供给油套。因此，可以减小油套所需的机械强度，以减小发动机气缸体的重量。

2. 发明申请

US20120138237A1 APPARATUS AND METHOD FOR DELAMINATING ADHESIVE FILM 审中-公开
标题翻译：胶粘剂薄膜分离装置及方法
公开(公告)号：US20120138237A1
公开(公告)日：2012-06-07
申请号：US13389650
申请日：2010-05-07
申请人： Takaaki Hirano
发明人： Takaaki Hirano
IPC分类号： B32B38/10
CPC分类号： G02F1/1303 , G02B5/3033 , G02F1/133528 , G02F2203/68 , Y10T156/11 , Y10T156/19
摘要： A delaminating apparatus (1) includes: a delamination stage (3) configured so that an LCD device (30) having an LCD panel is placed thereon; a wire (10) that is placed to extend along an entire outer periphery of a polarizing plate, so that the wire is inserted into a gap formed between the LCD panel and the polarizing plate in four corners of the polarizing plate; and a wire wind-up portion (5) configured to wind up the wire (10) to move the wire (10). By winding up the wire (10), the polarizing plate is separated from the LCD panel while moving the wire (10) between the polarizing plate and the LCD panel, whereby the polarizing plate is delaminated from the LCD panel.
摘要翻译：分层装置（1）包括：分层台（3），其配置成使具有LCD面板的LCD装置（30）放置在其上; 放置成沿着偏振片的整个外周延伸的线（10），使得所述线被插入到所述偏振片的四个角中的所述LCD面板和所述偏振片之间形成的间隙中; 以及线卷绕部分（5），其构造成卷绕所述线（10）以移动所述线（10）。通过卷绕线（10），偏振板在偏振板和LCD面板之间移动线（10）时与LCD面板分离，由此偏振板从LCD面板分层。

3. 发明申请

US20090098759A1 Connector Apparatus 有权
标题翻译：连接器装置
公开(公告)号：US20090098759A1
公开(公告)日：2009-04-16
申请号：US12251962
申请日：2008-10-15
申请人： Kenichi IKEYA , Kazumi Urano , Hideki Inoue , Takaaki Hirano , Nozomi Ito
发明人： Kenichi IKEYA , Kazumi Urano , Hideki Inoue , Takaaki Hirano , Nozomi Ito
IPC分类号： H01R13/627
CPC分类号： H01R13/5213
摘要： A connector apparatus comprises a connector, an annular member, and a cover member covering a rear surface of the connector. An engaging portion with a rear end surface is provided in the annular member. A step portion with a front end surface is provided in a rear portion of the connector. The cover member has a hook portion in the front end thereof. When the cover member covers the rear portion of the connector, the hook portion engages with the step portion. Thereafter, when the annular member is fixed to the connector, the rear end surface of the engaging portion and the front end surface of the step portion clamp the hook portion to prevent the hook portion from coming off.
摘要翻译：连接器装置包括连接器，环形构件和覆盖连接器后表面的盖构件。具有后端面的接合部设置在环状部件中。具有前端面的台阶部设置在连接器的后部。盖构件的前端具有钩部。当盖构件覆盖连接器的后部时，钩部与台阶部接合。此后，当环形构件固定到连接器上时，接合部分的后端表面和台阶部分的前端表面夹紧钩部，以防止钩部脱落。

4. 发明授权

US07411525B2 Sampling rate converting method and circuit 失效
标题翻译：采样率转换方法和电路
公开(公告)号：US07411525B2
公开(公告)日：2008-08-12
申请号：US11500971
申请日：2006-08-09
申请人： Takaaki Hirano
发明人： Takaaki Hirano
IPC分类号： H03M7/00
CPC分类号： H03H17/0621 , H03H17/0628 , H03H2218/06 , H03H2218/08
摘要： A sampling rate converting circuit receives plural pieces of input data having different sampling frequencies. A plurality of FIR circuits is shared to reduce a circuit area, and, in a case where a magnification ratio of an input frequency and an output frequency is not an integer, signal deterioration due to resampling is solved. An oversampling component performs oversampling on input data Fs1 and outputs output data Fs′. An input timing timer calculates an input/input time based on an input timing signal CK1. An output timing timer and an accumulator calculate an input/output time based on an output timing signal CK′ and the input timing signal CK1 and multiplies the input/output time by an oversampling multiple W to obtain a multiplied result. A divider divides the multiplied result by the input/input time to obtain a sampling position. A coefficient generator generates a filter coefficient based on the sampling position and supplies the filter coefficient to a multiplier.
摘要翻译：采样率转换电路接收具有不同采样频率的多条输入数据。共享多个FIR电路以减少电路面积，并且在输入频率和输出频率的倍率不是整数的情况下，解决了由于重采样引起的信号恶化。过采样分量对输入数据Fs 1进行过采样并输出输出数据Fs'。输入定时定时器基于输入定时信号CK 1计算输入/输入时间。输出定时定时器和累加器基于输出定时信号CK'和输入定时信号CK 1计算输入/输出时间，并将输入/输出时间乘以过采样倍数W以获得相乘结果。分频器将相乘结果除以输入/输入时间，以获得采样位置。系数发生器基于采样位置生成滤波器系数，并将滤波器系数提供给乘法器。

5. 发明申请

US20070046507A1 Sampling rate converting method and circuit 失效
标题翻译：采样率转换方法和电路
公开(公告)号：US20070046507A1
公开(公告)日：2007-03-01
申请号：US11500971
申请日：2006-08-09
申请人： Takaaki Hirano
发明人： Takaaki Hirano
IPC分类号： H03M7/00
CPC分类号： H03H17/0621 , H03H17/0628 , H03H2218/06 , H03H2218/08
摘要： A sampling rate converting circuit receives plural pieces of input data having different sampling frequencies. A plurality of FIR circuits is shared to reduce a circuit area, and, in a case where a magnification ratio of an input frequency and an output frequency is not an integer, signal deterioration due to resampling is solved. An oversampling component performs oversampling on input data Fs1 and outputs output data Fs′. An input timing timer calculates an input/input time based on an input timing signal CK1. An output timing timer and an accumulator calculate an input/output time based on an output timing signal CK′ and the input timing signal CK1 and multiplies the input/output time by an oversampling multiple W to obtain a multiplied result. A divider divides the multiplied result by the input/input time to obtain a sampling position. A coefficient generator generates a filter coefficient based on the sampling position and supplies the filter coefficient to a multiplier.
摘要翻译：采样率转换电路接收具有不同采样频率的多条输入数据。共享多个FIR电路以减少电路面积，并且在输入频率和输出频率的倍率不是整数的情况下，解决了由于重采样引起的信号恶化。过采样分量对输入数据Fs 1进行过采样并输出输出数据Fs'。输入定时定时器基于输入定时信号CK 1来计算输入/输入时间。输出定时定时器和累加器基于输出定时信号CK'和输入定时信号CK 1计算输入/输出时间，并将输入/输出时间乘以过采样倍数W以获得相乘结果。分频器将相乘结果除以输入/输入时间，以获得采样位置。系数发生器基于采样位置生成滤波器系数，并将滤波器系数提供给乘法器。

6. 发明授权

US08742596B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08742596B2
公开(公告)日：2014-06-03
申请号：US13416419
申请日：2012-03-09
申请人： Takaaki Hirano
发明人： Takaaki Hirano
IPC分类号： H01L23/488 , H01L21/50
CPC分类号： H01L23/562 , H01L23/481 , H01L23/522 , H01L23/564 , H01L25/0657 , H01L2224/16 , H01L2225/06541 , H01L2225/06565 , H01L2924/1461 , H01L2924/00
摘要： Disclosed herein is a semiconductor device including: a first laminate having a wiring layer formed on a substrate; a second laminate having a wiring layer formed on a substrate, a principal surface of the second laminate being bonded to a principal surface of the first laminate; a functional element disposed in at least one of the first laminate and the second laminate; and an air gap penetrating an interface between the first laminate and the second laminate, the air gap being disposed on an outside of a circuit formation region including the functional element in at least one of the first laminate and the second laminate as viewed from a direction perpendicular to the principal surfaces of the first laminate and the second laminate.
摘要翻译：本文公开了一种半导体器件，包括：第一层压体，其具有形成在基板上的布线层; 第二层压体，其具有形成在基板上的布线层，所述第二层叠体的主表面粘合到所述第一层叠体的主表面上; 设置在所述第一层压体和所述第二层压体中的至少一个中的功能元件; 以及穿过第一层压体和第二层压体之间的界面的气隙，当从方向观察时，气隙设置在包括第一层压体和第二层压体中的至少一个中的功能元件的电路形成区域的外侧垂直于第一层压板和第二层压板的主表面。

7. 发明授权

US5361365A Microprocessor for selectively performing cold and warm starts 失效
标题翻译：用于选择性地执行冷启动和暖启动的微处理器
公开(公告)号：US5361365A
公开(公告)日：1994-11-01
申请号：US24104
申请日：1993-02-23
申请人： Takaaki Hirano , Yoshinori Hashimoto
发明人： Takaaki Hirano , Yoshinori Hashimoto
IPC分类号： G06F9/26 , G06F9/32 , G06F9/445 , G06F9/06
CPC分类号： G06F9/4401 , G06F9/32
摘要： Upon power-on, a microprocessor is reset and initiates a cold start initialization program stored in ROM for initializing the microprocessor and associated peripherals. Thereafter, externally input control signals to the microprocessor indicate a desirable initialization operation for a warm start when the microprocessor is subsequently reset by an operator. A reset address generating circuit generates (1) a first address setting signal to set a first starting address of the initialization program for a cold start when receiving the reset signal at a power-ON or (2) a second address setting signal to set a second starting address of the initialization program corresponding to the warm start after the power-ON when receiving both a reset signal and a control signal generated externally by a user. A program counter is then set to an address corresponding to the inputted address setting signal. The microprocessor reads and executes initialization programs based on instructions in memory addressed by the program counter.
摘要翻译：上电时，微处理器复位并启动存储在ROM中的冷启动初始化程序，用于初始化微处理器和相关的外围设备。此后，当微处理器随后被操作者复位时，向微处理器的外部输入控制信号指示用于暖启动的期望的初始化操作。复位地址产生电路产生（1）第一地址设定信号，以在通电时接收到复位信号时设定用于冷启动的初始化程序的第一起始地址，或者（2）第二地址设定信号，当接收到复位信号和由用户外部产生的控制信号时，在上电之后对应于热启动的初始化程序的第二起始地址。然后将程序计数器设置为与输入的地址设置信号相对应的地址。微处理器根据由程序计数器寻址的存储器中的指令读取并执行初始化程序。

8. 发明授权

US07167034B2 Arrangement for correcting the phase of a data sampling clock signal during a period of sampling data in a received signal 失效
标题翻译：用于在接收信号的采样数据的周期期间校正数据采样时钟信号的相位的装置
公开(公告)号：US07167034B2
公开(公告)日：2007-01-23
申请号：US11038061
申请日：2005-01-21
申请人： Takaaki Hirano
发明人： Takaaki Hirano
IPC分类号： H03H3/00
CPC分类号： H04L7/0337 , G11C27/02 , H04L7/042
摘要： In a clock phase corrector appropriately correcting the phase of a data sampling clock signal, a series of shift registers responds to respective sampling clock signals to store received data sequentially. The stored data are duplicated by a comparator register in response to corresponding clock signals to output a demodulated signal. A corrector shift register is provided to store sampled data in response to a clock signal. The data thus stored are then held in a reception register as intended reception data. A comparator compares the demodulated signal with the intended reception data. Based upon a result from the comparison, a bit adder produces the number of inconsistent bits. Another comparator compares the number of inconsistent bits with the number of error acceptance bits stored in an error acceptance memory to generate a phase detection signal, in response to which a timing control adjusts the phase of a data sampling clock signal.
摘要翻译：在时钟相位校正器适当地校正数据采样时钟信号的相位的情况下，一系列移位寄存器响应相应的采样时钟信号以顺序地存储接收的数据。响应于相应的时钟信号，存储的数据由比较器寄存器复制以输出解调信号。提供校正器移位寄存器以响应于时钟信号来存储采样数据。然后将如此存储的数据作为预期的接收数据保存在接收寄存器中。比较器将解调信号与预期的接收数据进行比较。基于比较的结果，位加法器产生不一致比特的数量。另一个比较器将不一致位数与存储在错误接收存储器中的错误接收位数相比较，以产生相位检测信号，响应于此，定时控制调整数据采样时钟信号的相位。

9. 发明授权

US07597579B2 Connector apparatus 有权
标题翻译：连接器装置
公开(公告)号：US07597579B2
公开(公告)日：2009-10-06
申请号：US12251962
申请日：2008-10-15
申请人： Kenichi Ikeya , Kazumi Urano , Hideki Inoue , Takaaki Hirano , Nozomi Ito
发明人： Kenichi Ikeya , Kazumi Urano , Hideki Inoue , Takaaki Hirano , Nozomi Ito
IPC分类号： H01R13/627
CPC分类号： H01R13/5213
摘要： A connector apparatus comprises a connector, an annular member, and a cover member covering a rear surface of the connector. An engaging portion with a rear end surface is provided in the annular member. A step portion with a front end surface is provided in a rear portion of the connector. The cover member has a hook portion in the front end thereof. When the cover member covers the rear portion of the connector, the hook portion engages with the step portion. Thereafter, when the annular member is fixed to the connector, the rear end surface of the engaging portion and the front end surface of the step portion clamp the hook portion to prevent the hook portion from coming off.
摘要翻译：连接器装置包括连接器，环形构件和覆盖连接器后表面的盖构件。具有后端面的接合部设置在环状部件中。具有前端面的台阶部设置在连接器的后部。盖构件的前端具有钩部。当盖构件覆盖连接器的后部时，钩部与台阶部接合。此后，当环形构件固定到连接器上时，接合部分的后端表面和台阶部分的前端表面夹紧钩部，以防止钩部脱落。

10. 发明申请

US20120241981A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120241981A1
公开(公告)日：2012-09-27
申请号：US13416419
申请日：2012-03-09
申请人： Takaaki Hirano
发明人： Takaaki Hirano
IPC分类号： H01L23/488 , H01L21/50
CPC分类号： H01L23/562 , H01L23/481 , H01L23/522 , H01L23/564 , H01L25/0657 , H01L2224/16 , H01L2225/06541 , H01L2225/06565 , H01L2924/1461 , H01L2924/00
摘要： Disclosed herein is a semiconductor device including: a first laminate having a wiring layer formed on a substrate; a second laminate having a wiring layer formed on a substrate, a principal surface of the second laminate being bonded to a principal surface of the first laminate; a functional element disposed in at least one of the first laminate and the second laminate; and an air gap penetrating an interface between the first laminate and the second laminate, the air gap being disposed on an outside of a circuit formation region including the functional element in at least one of the first laminate and the second laminate as viewed from a direction perpendicular to the principal surfaces of the first laminate and the second laminate.
摘要翻译：本文公开了一种半导体器件，包括：第一层压体，其具有形成在基板上的布线层; 第二层压体，其具有形成在基板上的布线层，所述第二层叠体的主表面粘合到所述第一层叠体的主表面上; 设置在所述第一层压体和所述第二层压体中的至少一个中的功能元件; 以及穿过第一层压体和第二层压体之间的界面的气隙，当从方向观察时，气隙设置在包括第一层压体和第二层压体中的至少一个中的功能元件的电路形成区域的外侧垂直于第一层压板和第二层压板的主表面。

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