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1. 发明申请

US20100038722A1 MIS TRANSISTOR AND CMOS TRANSISTOR 有权
标题翻译： MIS晶体管和CMOS晶体管
公开(公告)号：US20100038722A1
公开(公告)日：2010-02-18
申请号：US12604015
申请日：2009-10-22
申请人： Takefumi NISHIMUTA , Hiroshi MIYAGI , Tadahiro OHMI , Shigetoshi SUGAWA , Akinobu TERAMOTO
发明人： Takefumi NISHIMUTA , Hiroshi MIYAGI , Tadahiro OHMI , Shigetoshi SUGAWA , Akinobu TERAMOTO
IPC分类号： H01L27/092
CPC分类号： H01L29/7851 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L29/045
摘要： A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.
摘要翻译：形成在半导体衬底上的MIS晶体管被假设为包括半导体衬底（702,910），该半导体衬底包括在主平面上的表面上具有至少两个不同晶面的突出部分（704,910B），栅极绝缘体（708 ，920B），用于覆盖构成所述突出部分的表面的所述至少两个不同晶面的每一个的至少一部分;栅电极（706,930B），包括在构成所述表面的所述至少两个不同晶面中的每一个上所述突出部分与所述至少两个不同平面夹住所述栅极绝缘体，以及形成在所述突出部分中的所述至少两个不同晶面中的每一个的单导电型扩散区域（710a，710b，910c，910d）并分别形成在栅电极的两侧。这种配置允许控制元件面积的增加和通道宽度的增加。

2. 发明申请

US20070071246A1 FM TRANSMITTER 有权
标题翻译： FM发射机
公开(公告)号：US20070071246A1
公开(公告)日：2007-03-29
申请号：US11460968
申请日：2006-07-28
申请人： Hiroshi MIYAGI
发明人： Hiroshi MIYAGI
IPC分类号： H04H5/00
CPC分类号： H04H20/88 , H03C3/40 , H04H20/48 , H04H20/72
摘要： An object of the present invention is to provide an FM transmitter in which the degree of freedom in parts selection is improved. The FM transmitter comprises: an oscillator 72 connected with a crystal oscillator 70; a clock generating circuit 50 which uses a signal formed by frequency-dividing an output signal of the oscillator 72 as a reference frequency signal fr1, and which generates a clock signal having a frequency of an integer multiple of the frequency of the reference frequency signal fr1; a DSP 20 which operates synchronously with the clock signal to perform stereo modulation processing, FM modulation processing, and IQ modulation processing to inputted stereo data by digital processing; a frequency synthesizer 60 which uses a signal formed by frequency-dividing the output signal of the oscillator 72 as a reference frequency signal fr2, and which generates a signal having a frequency of an integer multiple of the frequency of the reference frequency signal fr2; mixers 40 and 42 which mix signals outputted from the DSP 20 with signals generated by the frequency synthesizer 60, respectively; an adder 44 which adds outputs of the mixers 40 and 42; and an amplifier 46 which amplifies an output signal of the adder 44 and transmits the amplified signal from an antenna 48.
摘要翻译：本发明的目的是提供一种FM发射机，其中改善了部分选择的自由度。 FM发射机包括：与晶体振荡器70连接的振荡器72; 时钟发生电路50，其使用通过对振荡器72的输出信号进行分频而形成的信号作为参考频率信号fr 1，并且生成具有基准频率信号的频率的整数倍的频率的时钟信号 fr 1; 与时钟信号同步操作的DSP 20，通过数字处理对输入的立体声数据执行立体声调制处理，FM调制处理和IQ调制处理; 频率合成器60，其使用通过对振荡器72的输出信号进行分频而形成的信号作为参考频率信号fr 2，并产生具有基准频率信号fr 2的频率的整数倍的频率的信号 ; 混频器40和42分别将从DSP 20输出的信号与由频率合成器60产生的信号混合; 加法器44，其添加混频器40和42的输出; 以及放大加法器44的输出信号并从天线48发送放大信号的放大器46。

3. 发明申请

US20090213960A1 TRANSMITTER 审中-公开
标题翻译：发射机
公开(公告)号：US20090213960A1
公开(公告)日：2009-08-27
申请号：US12392825
申请日：2009-02-25
申请人： Takeshi IKEDA , Hiroshi MIYAGI
发明人： Takeshi IKEDA , Hiroshi MIYAGI
IPC分类号： H04L27/36 , H04L25/49 , H04L27/00
CPC分类号： H04L27/362 , H04L27/364
摘要： There are provided a BPF (15) for extracting an image frequency component from a modulating signal generated by modulating I and Q signals through a quadrature modulating portion (3), an energy detecting portion (16) for detecting an energy of the image frequency component, and an amplitude correcting portion (12) and a phase correcting portion (13) which correct an amplitude and a phase of the I signal to minimize the detected energy. By correcting the amplitude and the phase to minimize the energy of the image frequency component contained in the generated modulating signal without detecting amplitude and phase errors themselves of the I and Q signals, it is possible to accurately correct the amplitude and phase errors of the I and Q signals without an influence of a limit of precision in an error detection.
摘要翻译：提供了一种用于从通过正交调制部分（3）调制I和Q信号产生的调制信号中提取图像频率分量的BPF（15），用于检测图像频率分量的能量的能量检测部分（16）以及校正I信号的振幅和相位以使检测到的能量最小化的幅度校正部分（12）和相位校正部分（13）。通过校正幅度和相位来最小化包含在所产生的调制信号中的图像频率分量的能量，而不检测I和Q信号的幅度和相位误差本身，可以精确地校正I的振幅和相位误差和Q信号，而不受误差检测精度的限制。

4. 发明申请

US20050122243A1 Semiconductor integrated circuit for a radio apparatus and radio communication apparatus 审中-公开
标题翻译：一种用于无线电设备和无线电通信装置的半导体集成电路
公开(公告)号：US20050122243A1
公开(公告)日：2005-06-09
申请号：US10502833
申请日：2003-02-03
申请人： Hiroshi MIYAGI
发明人： Hiroshi MIYAGI
IPC分类号： H03J1/00 , H03J3/08 , H03J3/28 , H03J5/02 , H03M1/66 , H04B1/16 , H04B1/18 , H04B1/26 , H03M1/12
CPC分类号： H04B1/16 , H03J1/0033 , H04B1/18
摘要： Adjustment data of first and second tracking adjustment circuits 11 and 12 are set in latch circuits 21 and 22. The plurality of pieces of adjustment data latched by the latch circuits 21 and 22 are respectively output to one D/A converter 41 at different time intervals. The data are converted into a direct current control voltage in the D/A converter 41, and the control voltage is respectively held by voltage holding circuits of the first tracking adjustment circuit 11 and the second tracking adjustment circuit 12, and a tuning frequency is adjusted. After an optimum tuning frequency is obtained, the tuning data at that time is written to a nonvolatile memory within an IC, and the control voltage is supplied to each tuning circuit based on the tuning data stored in the nonvolatile memory.
摘要翻译：第一和第二跟踪调整电路11和12的调整数据被设置在锁存电路21和22中。由锁存电路21和22锁存的多个调节数据分别以不同的时间间隔输出到一个D / A转换器41。数据被转换成D / A转换器41中的直流控制电压，并且控制电压分别由第一跟踪调整电路11和第二跟踪调整电路12的电压保持电路保持，调谐频率被调整。在获得最佳调谐频率之后，此时的调谐数据被写入到IC内的非易失性存储器中，并且基于存储在非易失性存储器中的调谐数据将控制电压提供给每个调谐电路。

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