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1. 发明授权

US5543522A Process for preparing an ambient temperature molten salt using thionyl chloride 失效
标题翻译：使用亚硫酰氯制备环境温度熔盐的方法
公开(公告)号：US5543522A
公开(公告)日：1996-08-06
申请号：US295422
申请日：1994-08-25
申请人： Takayuki Kawahara , Hitoshi Suzuki , Asao Kominato
发明人： Takayuki Kawahara , Hitoshi Suzuki , Asao Kominato
IPC分类号： C07D213/20 , C07D233/90 , C07D521/00 , C07F5/06 , C25D3/66 , B65D85/18 , C07D213/18 , C25D21/18
CPC分类号： C07D213/20 , C07D231/12 , C07D233/56 , C07D249/08 , C07F5/069 , C25D3/665
摘要： There are disclosed a process for preparing an ambient temperature molten salt, which comprises treating an ambient temperature molten salt consisting essentially of 20 to 50 mole % of an aluminum halide and 80 to 50 mole % of an onium halide, containing oxygen-containing impurities originating from water with thionyl chloride anda process for preparing an ambient temperature molten salt for effecting aluminum electroplating, which comprises treating mixed ambient temperature molten salts consisting essentially of 30 to 50 mole % of an aluminum halide and 70 to 50 mole % of an onium halide, containing oxygen-containing impurities originating from water with thionyl chloride, and then adding aluminum halide to the molten salt to prepare an ambient temperature molten salt composition consisting essentially of 50 to 80 mole % of an aluminum halide and 50 to 20 mole % of an onium halide.
摘要翻译：公开了一种制备环境温度熔融盐的方法，该方法包括处理基本上由20至50摩尔％的铝卤化物和80至50摩尔％的卤化钇组成的环境温度的熔融盐，其含有含氧杂质从水中加入亚硫酰氯和制备用于进行铝电镀的环境温度熔融盐的方法，其包括处理基本上由30至50摩尔％的卤化铝和70至50摩尔％的卤化钇组成的混合的环境温度熔融盐，其中含有源自水的含氧杂质与亚硫酰氯，然后向熔融盐中加入卤化铝以制备基本上由50至80摩尔％卤化铝和50至20摩尔％的卤化铝组成的环境温度熔融盐组合物卤化铱

2. 发明授权

US08427864B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US08427864B2
公开(公告)日：2013-04-23
申请号：US13375751
申请日：2010-06-02
申请人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
发明人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
IPC分类号： G11C11/00
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1675 , H01L27/228
摘要： To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.
摘要翻译：为了在由MOS晶体管和隧道磁阻元件形成的SPRAM的存储单元上写入信息，向存储单元提供与在存储单元上写入信息所需的电流方向相反的方向的电流，然后，为存储单元提供写入所需的电流。以这种方式，即使当相同的信息被顺序地写入存储单元时，由于每当信息被重写时，两个方向上的电流成对地在存储单元的隧道磁阻元件中成对流动，所以，可以抑制隧道磁阻元件的形成。因此，可以提高SPRAM的可靠性。

3. 发明申请

US20130051134A1 SEMICONDUCTOR RECORDING DEVICE 失效
标题翻译：半导体记录装置
公开(公告)号：US20130051134A1
公开(公告)日：2013-02-28
申请号：US13643880
申请日：2011-04-05
申请人： Takayuki Kawahara , Riichiro Takemura , Takashi Ishigaki , Kiyoo Itoh
发明人： Takayuki Kawahara , Riichiro Takemura , Takashi Ishigaki , Kiyoo Itoh
IPC分类号： G11C11/16
CPC分类号： H01L27/228 , G11C7/1006 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697 , G11C11/5607
摘要： The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is, in the direction that causes reversal to either a parallel state or an anti-parallel state, applied to a memory cell having the plurality of TMR elements, and then a second current which is in the reverse direction from the first current and of which only the value needed to reverse the magnetoresistance state of at least one TMR element excluding the element requiring the maximum current among the plurality of TMR elements is applied to each, and multi-valued writing is performed.
摘要翻译：所公开的半导体记录装置使用自旋注入磁化 - 反转隧道磁阻元件（TMR元件）实现多值读取和写入。与在多个TMR元件之间需要最大电流以使其磁化反转的元件至少具有相同值的第一电流在引起反向并联状态或反并联状态的方向上，应用于具有多个TMR元件的存储单元，然后施加与第一电流相反方向的第二电流，并且其中只有反转至少一个TMR元件的磁阻状态所需的值，除了需要多个TMR元件中的最大电流被施加到每个，并且执行多值写入。

4. 发明申请

US20130033928A1 SEMICONDUCTOR STORAGE DEVICE AND DATA PROCESSING METHOD 有权
标题翻译：半导体存储器件和数据处理方法
公开(公告)号：US20130033928A1
公开(公告)日：2013-02-07
申请号：US13576913
申请日：2010-02-02
申请人： Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Nobuaki Kohinata
发明人： Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Nobuaki Kohinata
IPC分类号： G11C11/16
CPC分类号： G11C11/15 , G11C11/16 , G11C11/1653 , G11C11/1657 , G11C11/1675 , G11C11/1693
摘要： Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.
摘要翻译：由于非易失性RAM允许随机读取和写入操作，因此不需要擦除模式。然而，从系统侧，由于其非易失性特性，期望具有擦除模式。此外，擦除操作期望以低功耗高速进行。因此，提供了包含具有磁阻元件的多个存储单元MC的存储单元阵列COA和DTA，将一系列数据写入存储单元阵列COA和DTA，并且在擦除时，进行擦除操作通过将预定数据仅写入存储单元阵列COA来实现。

5. 发明授权

US08228724B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08228724B2
公开(公告)日：2012-07-24
申请号：US13345231
申请日：2012-01-06
申请人： Riichiro Takemura , Kenzo Kurotsuchi , Takayuki Kawahara
发明人： Riichiro Takemura , Kenzo Kurotsuchi , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： H01L47/00 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
摘要翻译：例如，一个存储单元被配置为使用两个存储单元晶体管和一个相变元件，通过将多个扩散层与位线平行地布置，在扩散层之间设置栅极以跨越位线，布置位线接触和源触点交替地布置到针对每个扩散层的位线方向上的多个扩散层，以及在源极触点上提供相变元件。此外，相位元件可以设置在位线触点上而不是源极触点。通过这种方式，例如，可以实现存储单元晶体管的驱动性的提高和面积的减小。

6. 发明申请

US20120081952A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20120081952A1
公开(公告)日：2012-04-05
申请号：US13375751
申请日：2010-06-02
申请人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
发明人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
IPC分类号： G11C11/16
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1675 , H01L27/228
摘要： To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.
摘要翻译：为了在由MOS晶体管和隧道磁阻元件形成的SPRAM的存储单元上写入信息，向存储单元提供与在存储单元上写入信息所需的电流方向相反的方向的电流，然后，为存储单元提供写入所需的电流。以这种方式，即使当相同的信息被顺序地写入存储单元时，由于每当信息被重写时，两个方向上的电流成对地在存储单元的隧道磁阻元件中成对流动，所以，可以抑制隧道磁阻元件的形成。因此，可以提高SPRAM的可靠性。

7. 发明申请

US20110194361A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110194361A1
公开(公告)日：2011-08-11
申请号：US13122732
申请日：2009-10-05
申请人： Takayuki Kawahara , Riichiro Takemura , Kazuo Ono
发明人： Takayuki Kawahara , Riichiro Takemura , Kazuo Ono
IPC分类号： G11C7/14 , G11C7/06
CPC分类号： G11C11/1675 , G11C7/065 , G11C7/12 , G11C7/18 , G11C8/14 , G11C11/16 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4094 , G11C11/4097 , H01L27/228
摘要： An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier.
摘要翻译：实现能够在小面积中提供必要且足够的电流的阵列配置，并且实现适合于TMR元件的温度特性的参考单元配置。在使用反转自旋转移切换的存储器中，多个程序驱动器沿着一个全局位线分开布置，并且一个读出放大器被提供给一个全局位线。 “1”和“0”被编程的参考单元由两个阵列和一个读出放大器共用。

8. 发明授权

US07732864B2 Semiconductor device and semiconductor integrated circuit using the same 失效
公开(公告)号：US07732864B2
公开(公告)日：2010-06-08
申请号：US11492054
申请日：2006-07-25
申请人： Takayuki Kawahara , Masanao Yamaoka
发明人： Takayuki Kawahara , Masanao Yamaoka
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L29/78645 , H01L29/78648
摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

9. 发明申请

US20100061169A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100061169A1
公开(公告)日：2010-03-11
申请号：US12620903
申请日：2009-11-18
申请人： Masanao YAMAOKA , Takayuki Kawahara
发明人： Masanao YAMAOKA , Takayuki Kawahara
IPC分类号： G11C7/00
CPC分类号： H03K19/0016 , G11C11/413
摘要： An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state.A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.
摘要翻译：本发明的目的是提供一种降低驱动电路的泄漏电流的技术，该驱动电路在处于其待机状态时必须保持电位（或信息）的驱动电路。本发明的半导体集成电路器件包括用于驱动电路块的驱动电路。该驱动电路由具有不同栅极氧化膜厚度的栅极的双栅极晶体管构成。当电路块处于其待机状态时，具有较薄栅极氧化膜的双栅极晶体管的栅极截止，并且具有较厚栅极氧化膜的栅极导通。这种布置允许减少电路块和驱动电路的漏电流，同时允许驱动电路传送或切断电路块的电力。

10. 发明授权

US07639525B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07639525B2
公开(公告)日：2009-12-29
申请号：US11541542
申请日：2006-10-03
申请人： Masanao Yamaoka , Takayuki Kawahara
发明人： Masanao Yamaoka , Takayuki Kawahara
IPC分类号： G11C11/00 , G11C5/06 , G11C11/34 , G11C5/14
CPC分类号： G11C11/412
摘要： A semiconductor memory device for reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode is provided. The semiconductor memory device also prevents an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area, and ensures stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
摘要翻译：一种半导体存储器件，用于降低使用按比例缩小晶体管的整个低功耗SRAM LSI电路的功耗，并且通过减少亚阈值漏电流和从该存储器单元流出的漏电流来增加对存储单元的读和写操作的稳定性漏电极到基板电极。半导体存储器件还防止了存储单元中的晶体管数量的增加，从而防止了单元面积的增加，并且确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作由控制驱动晶体管的BOX层下的阱的电位。

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