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1. 发明申请

US20110239931A1 EPITAXIAL SILICON WAFER AND FABRICATION METHOD THEREOF 有权
标题翻译：外延硅晶片及其制造方法
公开(公告)号：US20110239931A1
公开(公告)日：2011-10-06
申请号：US13164511
申请日：2011-06-20
申请人： Takayuki Dohi , Shinji Nakahara , Masaya Sakurai , Masato Sakai
发明人： Takayuki Dohi , Shinji Nakahara , Masaya Sakurai , Masato Sakai
IPC分类号： C30B25/20
CPC分类号： H01L21/02634 , C30B25/20 , C30B29/06 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L22/00 , H01L29/045 , H01L29/32 , H01L2924/0002 , Y10S117/902 , H01L2924/00
摘要： An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a orientation parallel to the {110} plane toward a direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.
摘要翻译：提供了一种外延硅晶片，其中外延层生长在具有从作为主表面的硅单晶的{110}面倾斜的平面的硅晶片上。在用于在其上生长外延层的硅晶片中，从平行于{110}平面朝向<100>的<100>取向测量，{110}面的倾斜角方位角在0至45度的范围内，方向。通过这样的布置，可以从具有高于{100}晶片的载流子迁移率（包括空穴和电子迁移率）的{110}晶片测量100nm或更小的LPD。此外，可以抑制{110}晶片中的表面粗糙度劣化。此外，可以测量{110}晶片的表面状态。此外，可以对{110}晶片进行质量评估。

2. 发明授权

US07989073B2 Epitaxial silicon wafer and fabrication method thereof 有权
标题翻译：外延硅晶片及其制造方法
公开(公告)号：US07989073B2
公开(公告)日：2011-08-02
申请号：US11850591
申请日：2007-09-05
申请人： Takayuki Dohi , Shinji Nakahara , Masaya Sakurai , Masato Sakai
发明人： Takayuki Dohi , Shinji Nakahara , Masaya Sakurai , Masato Sakai
IPC分类号： B32B9/00
CPC分类号： H01L21/02634 , C30B25/20 , C30B29/06 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L22/00 , H01L29/045 , H01L29/32 , H01L2924/0002 , Y10S117/902 , H01L2924/00
摘要： An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a orientation parallel to the {110} plane toward a direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100 } wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.
摘要翻译：提供了一种外延硅晶片，其中外延层生长在具有从作为主表面的硅单晶的{110}面倾斜的平面的硅晶片上。在用于在其上生长外延层的硅晶片中，从平行于{110}平面朝向<110>面的<100>取向测量，{110}面的倾斜角方位角在0至45度的范围内，方向。通过这样的布置，可以从具有高于{100}晶片的载流子迁移率（包括空穴和电子迁移率）的{110}晶片测量100nm或更小的LPD。此外，可以抑制{110}晶片中的表面粗糙度劣化。此外，可以测量{110}晶片的表面状态。此外，可以对{110}晶片进行质量评估。

3. 发明授权

US08152919B2 Epitaxial silicon wafer and fabrication method thereof 有权
标题翻译：外延硅晶片及其制造方法
公开(公告)号：US08152919B2
公开(公告)日：2012-04-10
申请号：US13164511
申请日：2011-06-20
申请人： Takayuki Dohi , Shinji Nakahara , Masaya Sakurai , Masato Sakai
发明人： Takayuki Dohi , Shinji Nakahara , Masaya Sakurai , Masato Sakai
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： H01L21/02634 , C30B25/20 , C30B29/06 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L22/00 , H01L29/045 , H01L29/32 , H01L2924/0002 , Y10S117/902 , H01L2924/00
摘要： An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a orientation parallel to the {110} plane toward a direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.
摘要翻译：提供了一种外延硅晶片，其中外延层生长在具有从作为主表面的硅单晶的{110}面倾斜的平面的硅晶片上。在用于在其上生长外延层的硅晶片中，从平行于{110}平面朝向<100>的<100>取向测量，{110}面的倾斜角方位角在0至45度的范围内，方向。通过这样的布置，可以从具有高于{100}晶片的载流子迁移率（包括空穴和电子迁移率）的{110}晶片测量100nm或更小的LPD。此外，可以抑制{110}晶片中的表面粗糙度劣化。此外，可以测量{110}晶片的表面状态。此外，可以对{110}晶片进行质量评估。

4. 发明申请

US20080057323A1 EPITAXIAL SILICON WAFER AND FABRICATION METHOD THEREOF 有权
标题翻译：外延硅晶片及其制造方法
公开(公告)号：US20080057323A1
公开(公告)日：2008-03-06
申请号：US11850591
申请日：2007-09-05
申请人： Takayuki Dohi , Shinji Nakahara , Masaya Sakurai , Masato Sakai
发明人： Takayuki Dohi , Shinji Nakahara , Masaya Sakurai , Masato Sakai
IPC分类号： B32B9/00 , C30B29/10
CPC分类号： H01L21/02634 , C30B25/20 , C30B29/06 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L22/00 , H01L29/045 , H01L29/32 , H01L2924/0002 , Y10S117/902 , H01L2924/00
摘要： An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a orientation parallel to the {110} plane toward a direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.
摘要翻译：提供了一种外延硅晶片，其中外延层生长在具有从作为主表面的硅单晶的{110}面倾斜的平面的硅晶片上。在用于在其上生长外延层的硅晶片中，从平行于{110}面朝向<110>面的<100>取向测量，{110}面的倾斜角方位角在0至45度的范围内，方向。通过这样的布置，可以从具有高于{100}晶片的载流子迁移率（包括空穴和电子迁移率）的{110}晶片测量100nm或更小的LPD。此外，可以抑制{110}晶片中的表面粗糙度劣化。此外，可以测量{110}晶片的表面状态。此外，可以对{110}晶片进行质量评估。

5. 发明申请

US20080057324A1 EPITAXIAL WAFER AND METHOD OF PRODUCING SAME 有权
标题翻译：外源波浪及其生产方法
公开(公告)号：US20080057324A1
公开(公告)日：2008-03-06
申请号：US11850599
申请日：2007-09-05
申请人： Shinji Nakahara , Masato Sakai , Takayuki Dohi
发明人： Shinji Nakahara , Masato Sakai , Takayuki Dohi
IPC分类号： B32B9/04 , C30B29/10
CPC分类号： C30B25/20 , C30B23/02 , C30B25/02 , C30B29/06 , C30B33/005 , H01L21/02024 , H01L21/76814
摘要： A method of producing an epitaxial wafer, comprising: performing epitaxial growth of silicon on a main surface of a wafer made of a silicon single crystal; performing surface flattening pretreatment of a main surface of the wafer using a treatment liquid of a predetermined composition at a temperature of 100° C. or less, thereby forming an oxide film of a predetermined thickness while removing particles adhered on the main surface of the wafer; and performing a surface polishing step where the main surface of the wafer is mirror polished.
摘要翻译：一种制造外延晶片的方法，包括：在由硅单晶构成的晶片的主表面上进行硅的外延生长; 使用预定组成的处理液在100℃以下的温度下对晶片的主表面进行表面平整预处理，从而形成预定厚度的氧化膜，同时除去附着在晶片主表面上的颗粒 ; 并进行表面抛光步骤，其中晶片的主表面被镜面抛光。

6. 发明授权

US09340900B2 Epitaxial wafer and method of producing same 有权
标题翻译：外延晶片及其制造方法
公开(公告)号：US09340900B2
公开(公告)日：2016-05-17
申请号：US11850599
申请日：2007-09-05
申请人： Shinji Nakahara , Masato Sakai , Takayuki Dohi
发明人： Shinji Nakahara , Masato Sakai , Takayuki Dohi
IPC分类号： H01L21/304 , C30B25/20 , C30B25/02 , C30B23/02 , C30B33/00 , H01L21/02 , H01L21/768 , C30B29/06
CPC分类号： C30B25/20 , C30B23/02 , C30B25/02 , C30B29/06 , C30B33/005 , H01L21/02024 , H01L21/76814
摘要： A method of producing an epitaxial wafer, comprising: performing epitaxial growth of silicon on a main surface of a wafer made of a silicon single crystal; performing surface flattening pretreatment of a main surface of the wafer using a treatment liquid of a predetermined composition at a temperature of 100° C. or less, thereby forming an oxide film of a predetermined thickness while removing particles adhered on the main surface of the wafer; and performing a surface polishing step where the main surface of the wafer is mirror polished.
摘要翻译：一种制造外延晶片的方法，包括：在由硅单晶构成的晶片的主表面上进行硅的外延生长; 使用预定组成的处理液在100℃以下的温度下对晶片的主表面进行表面平整预处理，从而形成预定厚度的氧化膜，同时除去附着在晶片主表面上的颗粒 ; 并进行表面抛光步骤，其中晶片的主表面被镜面抛光。

7. 发明申请

US20080110401A1 Susceptor For Vapor-Phase Growth Reactor 审中-公开
标题翻译：气相生长反应器的受体
公开(公告)号：US20080110401A1
公开(公告)日：2008-05-15
申请号：US11569139
申请日：2005-05-17
申请人： Takashi Fujikawa , Masayuki Ishibashi , Takayuki Dohi , Seiji Sugimoto
发明人： Takashi Fujikawa , Masayuki Ishibashi , Takayuki Dohi , Seiji Sugimoto
IPC分类号： C23C16/02
CPC分类号： H01L21/68735 , C23C16/4583 , C30B25/12 , H01L21/68785
摘要： In a susceptor (10) having a wafer pocket (101) for receiving a wafer W at the time of vapor-phase growth, the wafer pocket has at least a first pocket portion (102) for loading an outer circumferential portion of the wafer and a second pocket portion (103) formed to be lower than the first pocket and having a smaller diameter than that of the first pocket portion, and a fluid passage (105) having one end (105a) opening on a vertical wall (103a) of said second pocket portion and the other end (105b) opening on a back surface (104) or a side surface (106) of the susceptor is formed.
摘要翻译：在具有用于在气相生长时接收晶片W的晶片槽（101）的基座（10）中，晶片槽具有用于加载晶片的外圆周部分的至少第一凹部（102）形成为比所述第一凹部低的直径小于所述第一凹部的直径的第二凹部（103），以及具有在垂直壁（103a）上开口的一端（105a）的流体通路）和在所述基座的背面（104）或侧面（106）上开口的另一端（105b）形成。

8. 发明授权

US06971835B2 Vapor-phase epitaxial growth method 有权
标题翻译：气相外延生长法
公开(公告)号：US06971835B2
公开(公告)日：2005-12-06
申请号：US10323676
申请日：2002-12-20
申请人： Masayuki Ishibashi , Takayuki Dohi
发明人： Masayuki Ishibashi , Takayuki Dohi
IPC分类号： C23C16/44 , C23C16/458 , C30B25/12 , B65C49/07
CPC分类号： C30B25/12 , C23C16/4412 , C23C16/4585
摘要： A single opening is formed in a central portion of a susceptor of a vapor phase epitaxial growth system. Consequently, any dopant diffused off outwardly from the back surface of a wafer during an epitaxial growth process can be exhausted through the opening to the beneath side with respect to the susceptor. As a result, it may become difficult for auto-doping to be induced, even with no protective film formed on a back surface of the wafer. Uniformity in a dopant concentration in the surface may be improved and thus a resistivity may be made uniform. Further, since a temperature of the back surface of the wafer is measured through the opening, a heating temperature can be controlled stably, thus allowing a precise temperature control thereof. Consequently, the epitaxial film as well as the distribution of its resistivity may be made uniform across the entire wafer.
摘要翻译：在气相外延生长系统的基座的中心部分形成单个开口。因此，在外延生长过程期间从晶片背表面向外扩散的任何掺杂物可以通过开口相对于基座被耗尽到下侧。结果，即使没有在晶片的背面上形成保护膜，也可能难以引起自动掺杂。可以提高表面中掺杂剂浓度的均匀性，从而可以使电阻率均匀。此外，由于通过开口测量晶片的背面的温度，因此可以稳定地控制加热温度，从而允许其精确的温度控制。因此，可以在整个晶片上使外延膜以及其电阻率的分布均匀。

9. 发明授权

US08926754B2 Epitaxial growth susceptor 有权
公开(公告)号：US08926754B2
公开(公告)日：2015-01-06
申请号：US12461820
申请日：2009-08-25
申请人： Masayuki Ishibashi , John F. Krueger , Takayuki Dohi , Daizo Horie , Takashi Fujikawa
发明人： Masayuki Ishibashi , John F. Krueger , Takayuki Dohi , Daizo Horie , Takashi Fujikawa
IPC分类号： C23C16/00 , H01L21/306 , C30B25/12 , C23C16/458 , C30B29/06 , H01L21/687 , C23C16/455
CPC分类号： C30B25/12 , C23C14/50 , C23C14/54 , C23C16/45519 , C23C16/45521 , C23C16/4583 , C23C16/4584 , C23C16/4585 , C30B29/06 , H01L21/02381 , H01L21/20 , H01L21/2205 , H01L21/68735 , H01L21/68785
摘要： A susceptor for use in an epitaxial growth apparatus and method where a plurality of circular through-holes are formed in the bottom wall of a pocket in an outer peripheral region a distance of up to about ½ the radius toward the center of the circular bottom wall. The total opening surface area of these through-holes is 0.05 to 55% of the surface area of the bottom wall. The opening surface area of each of the through-holes provided at this outer peripheral region is 0.2 to 3.2 mm2 and the density of the through-holes is 0.25 to 25 per cm2. After a semiconductor wafer is mounted in the pocket, epitaxial growth is carried out while source gas and carrier gas (i.e., reactive gas) is made to flow on the upper surface side of the susceptor and carrier gas is made to flow on the lower surface side.

10. 发明申请

US20050000449A1 Susceptor for epitaxial growth and epitaxial growth method 审中-公开
标题翻译：外延生长和外延生长方法的受体
公开(公告)号：US20050000449A1
公开(公告)日：2005-01-06
申请号：US10483809
申请日：2002-12-23
申请人： Masayuki Ishibashi , John Krueger , Takayuki Dohi , Daizo Horie , Takashi Fujikawa
发明人： Masayuki Ishibashi , John Krueger , Takayuki Dohi , Daizo Horie , Takashi Fujikawa
IPC分类号： C23C16/44 , C23C16/455 , C23C16/458 , C30B25/12 , C30B29/06 , H01L21/687 , C23C16/00
CPC分类号： C30B25/12 , C23C14/50 , C23C14/54 , C23C16/45519 , C23C16/45521 , C23C16/4583 , C23C16/4584 , C23C16/4585 , C30B29/06 , H01L21/02381 , H01L21/20 , H01L21/2205 , H01L21/68735 , H01L21/68785
摘要： A susceptor for use in an epitaxial growth apparatus and method where a plurality of circular through-holes are formed in the bottom wall of a pocket in an outer peripheral region a distance of up to about ½ the radius toward the center of the circular bottom wall. The total opening surface area of these through-holes is 0.05 to 55% of the surface area of the bottom wall. The opening surface area of each of the through-holes provided at this outer peripheral region is 0.2 to 3.2 mm2 and the density of the through-holes is 0.25 to 25 per cm2. After a semiconductor wafer is mounted in the pocket, epitaxial growth is carried out while source gas and carrier gas (i.e., reactive gas) is made to flow on the upper surface side of the susceptor and carrier gas is made to flow on the lower surface side.
摘要翻译：一种用于外延生长装置和方法的感受体，其中多个圆形通孔形成在凹槽的底壁中的外围区域中，该圆形通孔的距离为圆形底壁的中心的半径的大约1/2 。这些通孔的总开口面积为底壁表面积的0.05〜55％。在该外周区域设置的各通孔的开口面积为0.2〜3.2mm 2，通孔的密度为每平方厘米0.25〜25。在将半导体晶片安装在口袋中之后，进行外延生长，同时源气体和载气（即，反应性气体）在基座的上表面侧流动，并使载气在下表面上流动侧。

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