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1. 发明申请

US20080169953A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080169953A1
公开(公告)日：2008-07-17
申请号：US12013855
申请日：2008-01-14
申请人： Takaya YAMAMOTO , Tatsuji Matsuura , Masumi Kasahara , Hideo Nakane , Junya Kudo , Yoshitaka Jingu
发明人： Takaya YAMAMOTO , Tatsuji Matsuura , Masumi Kasahara , Hideo Nakane , Junya Kudo , Yoshitaka Jingu
IPC分类号： H03M1/12 , H04L27/06
CPC分类号： H03M3/406 , H03M3/43 , H03M3/454
摘要： The A/D converter converting an analog input signal into a digital output signal is constructed with a band pass ΔΣ modulator. The band pass ΔΣ modulator includes: a resonator showing a band-pass characteristic at a predetermined frequency and an attenuation characteristic at another frequency; a quantizer; and a local D/A converter. A signal of difference between the analog input signal and a local analog signal of the local D/A converter is supplied to the resonator. The A/D converter further includes an adder for supplying the analog input signal to an input of the quantizer. In addition, signal transmission circuits for reducing the influence of spike noise of the quantizer on the input to the resonator are connected between an input of the adder and an input of resonator selectively. The A/D converter constructed with the band pass ΔΣ modulator is improved in S/N ratio.
摘要翻译：将模拟输入信号转换为数字输出信号的A / D转换器由带通DeltaSigma调制器构成。带通DeltaSigma调制器包括：表示预定频率的带通特性和另一频率的衰减特性的谐振器; 量化器和本地D / A转换器。模拟输入信号和本地D / A转换器的本地模拟信号之间的信号被提供给谐振器。 A / D转换器还包括用于将模拟输入信号提供给量化器的输入的加法器。此外，用于减小量化器的尖峰噪声对谐振器的输入的影响的信号传输电路被选择性连接在加法器的输入和谐振器的输入之间。用带通DeltaSigma调制器构成的A / D转换器的S / N比提高了。

2. 发明授权

US07583215B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07583215B2
公开(公告)日：2009-09-01
申请号：US12013855
申请日：2008-01-14
申请人： Takaya Yamamoto , Tatsuji Matsuura , Masumi Kasahara , Hideo Nakane , Junya Kudo , Yoshitaka Jingu
发明人： Takaya Yamamoto , Tatsuji Matsuura , Masumi Kasahara , Hideo Nakane , Junya Kudo , Yoshitaka Jingu
IPC分类号： H03M3/00
CPC分类号： H03M3/406 , H03M3/43 , H03M3/454
摘要： The A/D converter converting an analog input signal into a digital output signal is constructed with a band pass ΔΣ modulator. The band pass ΔΣ modulator includes: a resonator showing a band-pass characteristic at a predetermined frequency and an attenuation characteristic at another frequency; a quantizer; and a local D/A converter. A signal of difference between the analog input signal and a local analog signal of the local D/A converter is supplied to the resonator. The A/D converter further includes an adder for supplying the analog input signal to an input of the quantizer. In addition, signal transmission circuits for reducing the influence of spike noise of the quantizer on the input to the resonator are connected between an input of the adder and an input of resonator selectively. The A/D converter constructed with the band pass ΔΣ modulator is improved in S/N ratio.
摘要翻译：将模拟输入信号转换为数字输出信号的A / D转换器由带通DeltaSigma调制器构成。带通DeltaSigma调制器包括：表示预定频率的带通特性的谐振器和另一频率处的衰减特性; 量化器和本地D / A转换器。模拟输入信号和本地D / A转换器的本地模拟信号之间的信号被提供给谐振器。 A / D转换器还包括用于将模拟输入信号提供给量化器的输入的加法器。此外，用于减小量化器的尖峰噪声对谐振器的输入的影响的信号传输电路被选择性连接在加法器的输入和谐振器的输入之间。用带通DeltaSigma调制器构成的A / D转换器的S / N比提高了。

3. 发明申请

US20130249720A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20130249720A1
公开(公告)日：2013-09-26
申请号：US13744284
申请日：2013-01-17
申请人： Tatsuji Matsuura , Hideo Nakane , Masumi Kasahara , Ryuichi Ujiie , Keisuke Kimura , Oshima Takashi
发明人： Tatsuji Matsuura , Hideo Nakane , Masumi Kasahara , Ryuichi Ujiie , Keisuke Kimura , Oshima Takashi
IPC分类号： H03M1/06 , H03M1/10
CPC分类号： H03M1/06 , H03M1/1038 , H03M1/1071 , H03M1/123
摘要： A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing.
摘要翻译：具有用于通过数字校正处理将模拟输入信号转换成数字信号的A / D转换器的半导体集成电路器件面积减小。半导体集成电路器件具有第一A / D转换器和第二A / D转换器。在第一模式中，第一测试信号被输入到第一和第二A / D转换器，并且计算第一A / D转换器的第一校正系数和第二A / D转换器的第二校正系数。在第二模式中，第一A / D转换器通过对第一模拟信号进行第一数字校正处理而将第一模拟信号转换为第一数字信号，并且第二A / D转换器将第二模拟信号转换为第二数字信号通过对第二模拟信号进行第二数字校正处理。

4. 发明授权

US5684486A Flash A/D converter 失效
标题翻译：闪存A / D转换器
公开(公告)号：US5684486A
公开(公告)日：1997-11-04
申请号：US595999
申请日：1996-02-06
申请人： Koichi Ono , Masumi Kasahara , Eiki Imaizumi , Tatsuji Matsuura , Hisashi Okazawa
发明人： Koichi Ono , Masumi Kasahara , Eiki Imaizumi , Tatsuji Matsuura , Hisashi Okazawa
IPC分类号： H03M1/36
CPC分类号： H03M1/362
摘要： A flash A/D converter includes a plurality of master comparators for comparing a plurality of reference voltages and an input analog signal to absorb a current with a constant value from a non-inverted output or inverted output of each master comparator, a plurality of constant current sources, a plurality of load resistors and a plurality of slave comparators for outputting desired digital signals. The constant current value of one of the constant current sources coupled to a signal line coupled to the input of the slave comparator of a lower bit side is set to a value larger than that of one of the constant current sources coupled to a signal line coupled to the input of the slave comparator of a higher bit side. Thereby, it is possible to provide a flash A/D converter which has a low power consumption and a high speed.
摘要翻译：闪存A / D转换器包括用于比较多个参考电压的多个主比较器和输入模拟信号，以从每个主比较器的非反相输出或反相输出吸收具有常数值的电流，多个常数电流源，多个负载电阻器和用于输出期望数字信号的多个从属比较器。耦合到耦合到较低位侧的从比较器的输入的信号线的恒定电流源中的恒定电流值的恒定电流值被设置为大于耦合到耦合到信号线的恒定电流源之一的值到更高位侧的从比较器的输入。由此，能够提供低功耗，高速的闪存A / D转换器。

5. 发明授权

US08525712B2 Semiconductor integrated circuit and method of operating the same 有权
标题翻译：半导体集成电路及其操作方法
公开(公告)号：US08525712B2
公开(公告)日：2013-09-03
申请号：US13195144
申请日：2011-08-01
申请人： Takashi Oshima , Tatsuji Matsuura , Naoki Yada , Takahiro Miki , Akihiro Kitagawa , Tetsuo Matsui , Kunihiko Usui
发明人： Takashi Oshima , Tatsuji Matsuura , Naoki Yada , Takahiro Miki , Akihiro Kitagawa , Tetsuo Matsui , Kunihiko Usui
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , G01S7/4021 , G01S13/931 , H03M1/167 , H03M1/442
摘要： To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction.
摘要翻译：通过在安装在车载毫米波雷达装置中的半导体集成电路中减小内置A / D转换器的芯片所占用的面积来提高内置A / D转换器的分辨率， A / D转换器和MPU。在半导体集成电路中，由单个数字校正型A / D转换器对雷达装置的多个接收信号进行A / D转换。单个A / D转换器的数字校正型A / D转换器是从接收接口的多路复用器输出的接收信号顺序进行A / D转换的前景数字校正型A / D转换器。单个A / D转换器包括具有多个级联耦合转换器的流水线型A / D转换器。半导体集成电路包括校正信号生成单元，数字校正D / A转换器和用于数字校正的数字校正单元。

6. 发明授权

US07561094B2 Sequential comparison-type AD converter having small size and realizing high speed operation 失效
标题翻译：顺序比较型AD转换器，体积小，实现高速运行
公开(公告)号：US07561094B2
公开(公告)日：2009-07-14
申请号：US11889620
申请日：2007-08-15
申请人： Masao Hotta , Tatsuji Matsuura
发明人： Masao Hotta , Tatsuji Matsuura
IPC分类号： H03M1/38
CPC分类号： H03M1/0675 , H03M1/144 , H03M1/361
摘要： An analog-to-digital converter has a digital-to-analog converter, first, second and third comparators, and a sequential comparison register and control logic circuit. The digital-to-analog converter produces analog signals, the first, second and third comparators compare the input analog signal with first, second and third analog signals which are different from each other. Further, the sequential comparison register and control logic circuit controls the digital signals that are fed to the digital-to-analog converter from the first to third comparators, and outputs the digital signals as digital values obtained by subjecting the input analog signals to the analog-to-digital conversion.
摘要翻译：模拟 - 数字转换器具有数模转换器，第一，第二和第三比较器，以及顺序比较寄存器和控制逻辑电路。数模转换器产生模拟信号，第一，第二和第三比较器将输入模拟信号与彼此不同的第一，第二和第三模拟信号进行比较。此外，顺序比较寄存器和控制逻辑电路控制从第一至第三比较器馈送到数模转换器的数字信号，并将数字信号作为数字值输出，该数字值通过使输入的模拟信号经受模拟数字转换。

7. 发明授权

US4825287A Digital video signal processor 失效
标题翻译：数字视频信号处理器
公开(公告)号：US4825287A
公开(公告)日：1989-04-25
申请号：US063476
申请日：1987-06-18
申请人： Toru Baji , Tatsuji Matsuura , Toshiro Tsukada , Shinya Ohba
发明人： Toru Baji , Tatsuji Matsuura , Toshiro Tsukada , Shinya Ohba
IPC分类号： H04N5/14
CPC分类号： H04N5/14
摘要： According to the present invention, the number of elements of a signal processing circuit or the like can be drastically reduced by conducting a time-multiplex processing. In a transversal filter having a coefficient of symmetry of 16 taps, for example, the prior art requires about 58,000 transistors. In case four signal processing cores (i.e., SPC) having a function of four taps are used, the number of transistors required can be reduced to about 34,000 by a duplexing process. In case two SPCs having a function of eight taps are used, the number can be reduced to about 19,000 by a quadplexing process. In case, moreover, one SPC having a function of sixteen taps is used, the number can be reduced to about 13,000 by an octaplexing process. Here, the reason why the number of elements is not halved even if the number of the SPCs is halved is that the number of elements to be used in control circuits, memories and so on increases.
摘要翻译：根据本发明，通过进行时间复用处理，可以大大减少信号处理电路等的元件数量。在具有16个抽头的对称系数的横向滤波器中，例如，现有技术需要约58,000个晶体管。在使用具有四个抽头功能的四个信号处理核心（即，SPC）的情况下，通过双工处理，所需的晶体管数量可以减少到约34,000个。在使用具有八个抽头功能的两个SPC的情况下，通过四重处理可将数量减少到约19,000个。此外，在使用具有十六个抽头功能的一个SPC的情况下，也可以通过八次打印处理将数量减少到约13,000个。这里，即使SPC的数量减半，元件的数量不减半的原因在于控制电路，存储器等中要使用的元件的数量增加。

8. 发明授权

US07961821B2 Communication semiconductor integrated circuit, radio communication system, and adjustment method of gain and offset 有权
标题翻译：通信半导体集成电路，无线电通信系统以及增益和偏移调整方法
公开(公告)号：US07961821B2
公开(公告)日：2011-06-14
申请号：US12276532
申请日：2008-11-24
申请人： Toshihito Habuka , Naoto Inokawa , Kiyoharu Ozaki , Tatsuji Matsuura , Koichi Yahagi
发明人： Toshihito Habuka , Naoto Inokawa , Kiyoharu Ozaki , Tatsuji Matsuura , Koichi Yahagi
IPC分类号： H04L27/08
CPC分类号： H04L27/3809 , H03G3/3068 , H04L25/061 , H04L27/2647
摘要： A D.C. offset canceling and gain adjusting techniques permitting completion of correction of D.C. offsets and gain adjustment of amplifiers for amplifying reception signals in a radio communication system are provided. A communication semiconductor integrated circuit has a plurality of low-pass filters and variable gain amplifiers which are alternately connected in multiple stages, and high gain amplifier circuits for amplifying reception signals to a predetermined amplitude level. Offset cancellation values are generated by detecting D.C. offsets of amplifiers for amplifying reception signals according to a set gain, and stored into a memory, and read out of the memory to cancel the D.C. offsets of the amplifiers when starting reception and altering the gain. Gain setting in a high gain amplifying section is accomplished using rough and precise settings.
摘要翻译：提供了D.C.偏移消除和增益调整技术，其允许完成D.C.偏移的校正和用于在无线电通信系统中放大接收信号的放大器的增益调整。通信半导体集成电路具有多个交替连接的多个低通滤波器和可变增益放大器，以及用于将接收信号放大到预定幅度电平的高增益放大器电路。通过根据设定的增益检测用于放大接收信号的放大器的直流偏移量，并将其存储到存储器中，并从存储器中读出以消除开始接收和改变增益时放大器的直流偏移量来产生偏移抵消值。高增益放大部分的增益设置是通过粗略和精确的设置实现的。

9. 发明申请

US20090225631A1 Time-to-digital converter 有权
标题翻译：时间到数字转换器
公开(公告)号：US20090225631A1
公开(公告)日：2009-09-10
申请号：US12382056
申请日：2009-03-06
申请人： Kazuya shimizu , Masato Kaneta , Haruo Kobayashi , Tatsuji Matsuura , Katsuyoshi Yagi , Akira Abe , Koichiro Mashiko
发明人： Kazuya shimizu , Masato Kaneta , Haruo Kobayashi , Tatsuji Matsuura , Katsuyoshi Yagi , Akira Abe , Koichiro Mashiko
IPC分类号： G04F10/00
CPC分类号： G04F10/06
摘要： A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a difference between the first delay amount and the second delay amount is smaller than the first delay amount and the second delay amount.
摘要翻译：公开了具有小尺度电路和高分辨率的TDC电路，其是检测相对于待测信号的参考时钟的相位的时间到数字转换器，包括第一延迟线，其中多个具有第一延迟量的第一延迟元件被串联连接，第二延迟线组连接到第一延迟线的多个连接节点或第一级中的输入节点，并且其中至少一个或多个第二延迟具有与第一延迟量不同的第二延迟量的元件串联连接;多个判断电路，用于判断待测信号的变化边沿是否相对于从...的延迟时钟输出的变化沿提前或延迟第一延迟元件和第二延迟元件，以及操作电路，其从判断器计算相对于待测信号的变化边沿的参考时钟的相位 t结果，其中第一延迟量和第二延迟量之间的差小于第一延迟量和第二延迟量。

10. 发明授权

US07286074B2 Semiconductor integrated circuit for communication including analog-to-digital conversion circuit 失效
标题翻译：用于通信的半导体集成电路包括模数转换电路
公开(公告)号：US07286074B2
公开(公告)日：2007-10-23
申请号：US11189701
申请日：2005-07-27
申请人： Junya Kudoh , Kouichi Yahagi , Tatsuji Matsuura
发明人： Junya Kudoh , Kouichi Yahagi , Tatsuji Matsuura
IPC分类号： H03M1/34
CPC分类号： H03M1/0845 , H03M1/365 , H03M1/44 , H03M1/804 , H03M3/368 , H03M3/454
摘要： A semiconductor integrated circuit having a built-in A/D conversion circuit which enables, where the A/D conversion circuit is to be built into a semiconductor chip, the required capacitance of the stabilization capacitor to be connected to the output terminals of reference voltage generators for generating reference voltages to be reduced is to be provided to contribute to preventing the number of external terminals and the chip size from increasing. A semiconductor integrated circuit having a built-in differential type A/D conversion circuit comprising a differential amplifier, a local A/D converter and local D/A converters, further provided with a first reference voltage generator for generating a first reference voltage and a second reference voltage generator for generating a second reference voltage both for use by the local A/D converter, wherein the first reference voltage generator and the second reference voltage generator are provided as common reference voltage generators with a reference voltage generator for generating a first reference voltage and a second reference voltage both for use by the local D/A converters, and a capacitance element for stabilizing the generated reference voltages is connected between the output terminal of the first reference voltage generator and that of the second reference voltage generator.
摘要翻译：一种具有内置A / D转换电路的半导体集成电路，其能够将A / D转换电路内置于半导体芯片中，将要连接到参考电压的输出端的稳定电容器的所需电容提供用于产生要减小的参考电压的发生器用于防止外部端子的数量和芯片尺寸的增加。一种具有内置差分型A / D转换电路的半导体集成电路，包括差分放大器，局部A / D转换器和本地D / A转换器，还具有用于产生第一参考电压的第一参考电压发生器和第二参考电压发生器，用于产生由本地A / D转换器使用的第二参考电压，其中第一参考电压发生器和第二参考电压发生器作为公共参考电压发生器提供，其具有用于产生第一参考的参考电压发生器电压和第二参考电压都被本地D / A转换器使用，并且用于稳定所产生的参考电压的电容元件连接在第一参考电压发生器的输出端和第二参考电压发生器的输出端之间。

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