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1. 发明授权

US06627996B1 Semiconductor device having fluorine containing silicon oxide layer as dielectric for wiring pattern having anti-reflective layer and insulating layer thereon 有权
标题翻译：具有含氟氧化硅层的半导体器件作为具有抗反射层和绝缘层的布线图案的电介质
公开(公告)号：US06627996B1
公开(公告)日：2003-09-30
申请号：US09680437
申请日：2000-10-06
申请人： Takashi Yokoyama , Yoshiaki Yamada , Koji Kishimoto
发明人： Takashi Yokoyama , Yoshiaki Yamada , Koji Kishimoto
IPC分类号： H01L2348
CPC分类号： H01L21/02131 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31629 , H01L21/76829 , H01L21/76834 , H01L21/76837 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with satisfactory bonding ability of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for burying wiring space portions. The semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is formed by etching the anti-reflection layer and the metal layer while taking the patterned insulation layer as a mask and leaving the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface thereby.
摘要翻译：一种半导体器件，其具有令人满意的布线空间部分等离子体SiOF氧化物层的接合能力和掩埋能力。半导体衬底，在金属层上形成难熔金属或其化合物的抗反射层，并在抗反射层上形成绝缘层。之后，对绝缘层进行构图，并且通过在将图案化绝缘层作为掩模并且将抗反射层和绝缘层留在布线上的同时蚀刻抗反射层和金属层来形成布线。随后，图案化的布线被掩埋成SiOF层作为含氟的Si氧化物层，以及上表面上的防反射层和绝缘层。

2. 发明授权

US06130154A Semiconductor device and fabrication process thereof 失效
标题翻译：半导体器件及其制造工艺
公开(公告)号：US06130154A
公开(公告)日：2000-10-10
申请号：US49931
申请日：1998-03-30
申请人： Takashi Yokoyama , Yoshiaki Yamada , Koji Kishimoto
发明人： Takashi Yokoyama , Yoshiaki Yamada , Koji Kishimoto
IPC分类号： H01L21/28 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/4763 , H01L21/31
CPC分类号： H01L21/02131 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31629 , H01L21/76829 , H01L21/76834 , H01L21/76837 , H01L2924/0002
摘要： A semiconductor device with satisfactory bonding avility of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for buring wiring space portions. The semiconductor device is deposited by forming a metal layer to be a base of wiring on a semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is patterned by etching the anti-reflection layer and the metal layer to be the base of the wiring with taking the patterned insulation layer as a mask with leasing the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface.
摘要翻译：一种半导体器件，其具有令人满意的等离子体SiOF氧化物层的接合能力，并且具有良好的掩埋布线空间部分的掩埋能力。通过在半导体衬底上形成作为布线基底的金属层，在金属层上形成难熔金属或其化合物的抗反射层，并在抗反射层上形成绝缘层来沉积半导体器件层。之后，对绝缘层进行图案化，并且通过将抗反射层和金属层作为布线的基底进行蚀刻，以图案化的绝缘层为掩模，通过将抗反射层和绝缘体布线上的层。接着，将图案化的布线与上部表面上的防反射层和绝缘层一起作为包含氟的SiO 2层作为Si氧化物层进行掩埋。

3. 发明授权

US06287956B1 Multilevel interconnecting structure in semiconductor device and method of forming the same 失效
公开(公告)号：US06287956B1
公开(公告)日：2001-09-11
申请号：US09066115
申请日：1998-04-23
申请人： Takashi Yokoyama , Yoshiaki Yamada , Koji Kishimoto
发明人： Takashi Yokoyama , Yoshiaki Yamada , Koji Kishimoto
IPC分类号： H01L214763
摘要： A multilevel interconnecting structure includes a plurality of interconnecting layers formed on a semiconductor substrate, a fluorine-doped oxide film for burying portions between the interconnecting layers, and an oxide film formed on the fluorine-doped oxide film, having a planarized surface, and not containing fluorine. A method of forming the multilevel interconnecting structure is also disclosed.

4. 发明授权

US6093637A Method of making a multi-layer interconnection structure 失效
标题翻译：制作多层互连结构的方法
公开(公告)号：US6093637A
公开(公告)日：2000-07-25
申请号：US946786
申请日：1997-10-08
申请人： Koji Kishimoto , Yoshiaki Yamada
发明人： Koji Kishimoto , Yoshiaki Yamada
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/02126 , H01L21/02164 , H01L21/022 , H01L21/02216 , H01L21/02271 , H01L21/02274 , H01L21/02282 , H01L21/31612 , H01L21/76801 , H01L21/76828 , H01L21/76837 , H01L23/5329 , H01L21/31055 , H01L2924/0002
摘要： A multi-layer interconnection structure in a semiconductor device has a interlevel dielectric layer of three SiO.sub.2 films. The first SiO.sub.2 film has a small thickness not lower than 25 nm and is formed by a dual-frequency plasma enhanced CVD process using alkoxysilane as a reactive gas. The second SiO.sub.2 film has a large thickness ranging between 300 and 800 nm and is formed on the first SiO.sub.2 film by an atmospheric pressure CVD process using a mixture of alkoxysilane and ozone as a reactive gas. The third SiO.sub.2 film has a thickness of 50 nm and is flattened by an etch-back process of the same together with an overlying sacrificial spin-on glass film. A second layer interconnect pattern is formed on or above the flattened third SiO.sub.2 film with an excellent reliability.
摘要翻译：半导体器件中的多层互连结构具有三个SiO 2膜的层间电介质层。第一SiO 2膜具有不小于25nm的小厚度，并且通过使用烷氧基硅烷作为反应气体的双频等离子体增强CVD工艺形成。第二SiO 2膜具有在300和800nm之间的大厚度，并且通过使用烷氧基硅烷和臭氧的混合物作为反应气体的大气压CVD法在第一SiO 2膜上形成。第三SiO 2膜具有50nm的厚度，并且通过其上的牺牲旋涂玻璃膜的回蚀工艺被平坦化。第二层互连图案形成在平坦化的第三SiO 2膜上或上方，具有优异的可靠性。

5. 发明授权

US06294467B1 Process for forming fine wiring 有权
标题翻译：形成精细布线的工艺
公开(公告)号：US06294467B1
公开(公告)日：2001-09-25
申请号：US09270855
申请日：1999-03-17
申请人： Takashi Yokoyama , Koji Kishimoto
发明人： Takashi Yokoyama , Koji Kishimoto
IPC分类号： H01L2144
CPC分类号： H01L21/76826 , H01L21/76823 , H01L21/76843 , H01L21/76856 , H01L21/76859 , H01L21/76861 , H01L21/76873 , H01L21/76877
摘要： The present invention is directed to a process for manufacturing a semiconductor device. It includes a step for forming a fine wiring, and provides a process for uniformly and positively forming a film of a barrier metal, such as tantalum, for preventing the metal, such as copper, which becomes the first material for the wiring, from diffusing into a silicon oxide film. The process involves depositing an oxide of a barrier metal on a substrate which is formed with a via hole by a process such as CVD process. A high quality barrier metal film is formed by reducing the oxide by applying a negative potential to the oxide in a solution in which hydrogen ions are present. Subsequently an embedded wiring is formed by embedding the main metal by a plating process and the like and polishing to remove unnecessary portions.
摘要翻译：本发明涉及半导体器件的制造方法。它包括用于形成精细布线的步骤，并且提供了用于均匀且积极地形成诸如钽的阻挡金属的膜的方法，以防止成为布线的第一材料的诸如铜的金属（例如铜）扩散成为氧化硅膜。该方法包括通过诸如CVD工艺的工艺在形成有通孔的基板上沉积阻挡金属的氧化物。通过在存在氢离子的溶液中对氧化物施加负电位来还原氧化物，形成高质量的阻挡金属膜。随后，通过电镀工艺等包埋主金属并抛光以除去不必要的部分来形成嵌入布线。

6. 发明授权

US08258407B2 Wiring board and method of preventing high voltage damage 有权
标题翻译：接线板及防止高压损坏的方法
公开(公告)号：US08258407B2
公开(公告)日：2012-09-04
申请号：US12238729
申请日：2008-09-26
申请人： Koji Kishimoto
发明人： Koji Kishimoto
IPC分类号： H05K1/00 , H05K1/02 , H05K1/16 , H05K1/14 , H05K7/00
CPC分类号： H05K1/0268 , H05K1/026 , H05K1/111
摘要： A wiring board is provided to protect an electronic device from static electricity and lightning surge without reducing packaging density. A wiring board is provided with a first wiring pattern (3) including mounting pads (8, 10), on which an electronic device (5) is mounted, a second wiring pattern (21) having lower impedance than the first wiring pattern (3), ICT wirings (13, 15) extending from the mounting pads (8, 10) of the first wiring pattern (3), and ICT pads (17, 19) formed at distal ends of the ICT wirings (13, 15). The ICT wirings (13, 15) extend towards the second wiring pattern (21) so that the ICT pads (13, 15) are in the vicinity of the second wiring pattern (21), and discharge gaps (G) are formed between the ICT pads (13, 15) and the second wiring pattern (21).
摘要翻译：提供了一种布线板，用于保护电子设备免受静电和雷电浪涌的影响，而不会降低包装密度。布线板设置有第一布线图案（3），第一布线图案（3）包括安装有电子设备（5）的安装垫（8,10），具有比第一布线图案（3）低的阻抗的第二布线图案），从第一布线图案（3）的安装垫（8,10）延伸的ICT布线（13,15）以及形成在ICT布线（13,15）的远端处的ICT垫（17,19）。 ICT布线（13,15）朝向第二布线图案（21）延伸，使得ICT垫片（13,15）在第二布线图案（21）附近，并且排出间隙（G）形成在第二布线图案 ICT垫（13,15）和第二布线图案（21）。

7. 发明授权

US08330676B2 Plasma tube array-type display device and luminance correcting method 失效
标题翻译：等离子管阵列式显示装置及亮度校正方法
公开(公告)号：US08330676B2
公开(公告)日：2012-12-11
申请号：US12486028
申请日：2009-06-17
申请人： Koji Shinohe , Koji Kishimoto , Tetsuya Makino , Hitoshi Hirakawa , Kenji Awamoto
发明人： Koji Shinohe , Koji Kishimoto , Tetsuya Makino , Hitoshi Hirakawa , Kenji Awamoto
IPC分类号： G09G3/28
CPC分类号： G09G3/288 , G09G3/2983 , G09G2320/0233 , G09G2320/0693
摘要： This invention provides a plasma tube array-type display device and a luminance correcting method realizing reduced variations in luminance values of a plasma tube array. A gradient of the luminance value in the longitudinal direction of one plasma tube is calculated on the basis of the obtained luminance value at a plurality of positions in the longitudinal direction of at least one plasma tube. A difference of the luminance value of each plasma tube obtained at the same relative position. On the basis of the gradient of the luminance value and the difference of the luminance value of each plasma tube at the same relative position, a correction luminance value in each discharge cell in the longitudinal direction of each of the plurality of plasma tubes is calculated.
摘要翻译：本发明提供一种等离子体管阵列型显示装置和实现等离子体管阵列的亮度变化的亮度校正方法。基于在至少一个等离子体管的纵向上的多个位置处获得的亮度值来计算一个等离子体管的纵向的亮度的梯度。在相同相对位置获得的等离子体管的亮度值的差异。基于相同相对位置处的亮度值的梯度和等离子体管的亮度差的差异，计算出各个等离子体管的长度方向上的各放电单元的校正亮度值。

8. 发明授权

US5891234A Spin on glass material and method for forming a semiconductor device by using improved spin on glass material 失效
标题翻译：通过使用玻璃材料上的旋转来旋转玻璃材料和形成半导体器件的方法
公开(公告)号：US5891234A
公开(公告)日：1999-04-06
申请号：US619086
申请日：1996-03-21
申请人： Kenichi Koyanagi , Koji Kishimoto , Tetsuya Homma
发明人： Kenichi Koyanagi , Koji Kishimoto , Tetsuya Homma
IPC分类号： H01L21/768 , C03C1/00 , H01L21/316 , C09D183/04
CPC分类号： C03C1/008
摘要： A spin on glass composition which includes in a solvent as a main component alkoxysilane represented by H.sub.n Si(OR).sub.4-n, where n is 1, 2, or 3 and R is an alkyl group. Water or alcohol is available as a solvent. It is preferable to add the above alkoxysilane with at least any one of a phosphorus compound, boron compound and a germanium compound. It is also preferable to add the above alkoxysilane not only with tetraalkoxysilane Si(OR).sub.4, where R is an alkyl group, but also with at least any one of phosphorus compound, boron compound and germanium compound.
摘要翻译：在由H n Si（OR）4-n表示的主要成分的烷氧基硅烷的溶剂中包括n为1,2或3，R为烷基的旋涂玻璃组合物。水或醇可作为溶剂使用。优选使用磷化合物，硼化合物和锗化合物中的至少一种添加上述烷氧基硅烷。另外，优选不仅与四烷氧基硅烷Si（OR）4（其中R为烷基），而且还与磷化合物，硼化合物和锗化合物中的至少一种相加。

9. 发明授权

US4789381A Fiber treating process and composition used therefor 失效
标题翻译：纤维处理工艺及其组合物
公开(公告)号：US4789381A
公开(公告)日：1988-12-06
申请号：US41404
申请日：1987-04-23
申请人： Shigeki Oshiyama , Koji Kishimoto , Takeshi Hirota , Shigetoshi Suzue , Hiroyoshi Hiramatsu , Kiyoaki Yoshikawa , Nobuyuki Suzuki
发明人： Shigeki Oshiyama , Koji Kishimoto , Takeshi Hirota , Shigetoshi Suzue , Hiroyoshi Hiramatsu , Kiyoaki Yoshikawa , Nobuyuki Suzuki
IPC分类号： D06M13/192 , D06M13/224 , D06M13/10
CPC分类号： D06M13/224 , D06M13/192
摘要： Disclosed herein is a fiber treating process which comprises treating fibers.An ester formed by the union of an polybasic carboxylic acid and a compound represented by the formula below ##STR1## where R.sub.1 and R.sub.2 represent C.sub.4 -C.sub.18 alkyl groups; AO represents a C.sub.2 -C.sub.4 alkyleneoxide group; and n represents an integer of 0 to 30.

10. 发明申请

US20090316411A1 DISPLAY DEVICE 失效
标题翻译：显示设备
公开(公告)号：US20090316411A1
公开(公告)日：2009-12-24
申请号：US12486814
申请日：2009-06-18
申请人： Katsuhiko ITAMASU , Koji Kishimoto , Koji Shinohe , Manabu Ishimoto , Hitoshi Hirakawa , Kenji Awamoto
发明人： Katsuhiko ITAMASU , Koji Kishimoto , Koji Shinohe , Manabu Ishimoto , Hitoshi Hirakawa , Kenji Awamoto
IPC分类号： F21V13/02 , H01J17/49
CPC分类号： H01J11/18
摘要： This invention provides a display device capable of maintaining a high image quality of a display image even when a plurality of plasma tube array-type display sub-modules is joined horizontally to one another. A display device comprises a plasma tube array-type display sub-module in which a plurality of plasma tubes 31, 31, . . . , are arranged in parallel being held between an address electrode support sheet where address electrodes are formed and a display electrode support sheet 35 where display electrodes are formed, wherein the plurality of plasma tube array-type display sub-modules 30, 30, . . . , are joined horizontally to one another so that an interval between the adjacent plasma tube array-type display sub-modules 30, 30, . . . , and a clearance between the adjacent plasma tubes 31, 31 are substantially equal.
摘要翻译：本发明提供即使当等离子体管阵列型显示子模块彼此水平连接时，也能够保持显示图像的高图像质量的显示装置。显示装置包括等离子体管阵列型显示子模块，其中多个等离子体管31,31，...，。。平行地配置，保持在形成有寻址电极的寻址电极支撑片和形成显示电极的显示电极支撑片35之间，其中多个等离子体管阵列型显示子模块30,30。。。彼此水平相连，使得相邻的等离子体管阵列型显示子模块30,30，30之间的间隔。。。，相邻等离子体管31,31之间的间隙基本相等。

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