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1. 发明授权

US06985501B2 Device and method for reducing delay jitter in data transmission 失效
公开(公告)号：US06985501B2
公开(公告)日：2006-01-10
申请号：US09827639
申请日：2001-04-06
申请人： Takashi Suzuki , Toshiro Kawahara , Masashi Morioka , Nobuhiko Naka
发明人： Takashi Suzuki , Toshiro Kawahara , Masashi Morioka , Nobuhiko Naka
IPC分类号： H04J3/06 , H04L12/26
CPC分类号： H04L65/80 , H04L12/6418 , H04L29/06027 , H04L47/10 , H04L47/2416 , H04L47/28 , H04L2012/6472 , H04L2012/6489
摘要： A delay unit 103 adds holding time that has been set by a holding time setting unit 104 to a received data. The holding time is computed based on delay time of received data and the minimum delay time of data received up to a certain point for the purpose of reducing a total delay time. The delay time is estimated in a delay time estimating unit 106 from the difference between a reception time of a packet counted based on an internal clock generator 107 and a time designated by a time stamp in the received packet.

2. 发明授权

US06522665B1 Data sequence generator, transmitter, information data decoder, receiver, transmitter-receiver, data sequence generating method, information data decoding method, and recording medium 有权
标题翻译：数据序列发生器，发射机，信息数据解码器，接收机，发射机 - 接收机，数据序列生成方法，信息数据解码方法和记录介质
公开(公告)号：US06522665B1
公开(公告)日：2003-02-18
申请号：US09269919
申请日：1999-04-01
申请人： Takashi Suzuki , Toshio Miki , Toshiro Kawahara , Nobuhiko Naka
发明人： Takashi Suzuki , Toshio Miki , Toshiro Kawahara , Nobuhiko Naka
IPC分类号： H04J322
CPC分类号： H04L1/008 , G11B20/12 , G11B20/1217 , G11B20/1833 , G11B27/10 , G11B27/3027 , H03M13/09 , H04L1/0072 , H04L1/08
摘要： The probability of frame destruction is lowered while suppressing the redundancy of the transmission data. On the transmitting side, a predetermined unique word is contained in a frame n for storing the n-th data, and header information n, frame length information and header information n−1 of the frame n−1 one frame before the frame n are subjected to error-correcting coding, contained in the frame n, and transmitted. On the receiving side, the header of the frame n is received. When the frame length information is transmitted with error, the timing is specified by detecting the unique word and header information in the next frame n+1. When the header of the frame n is not successfully decoded, the information data of the frame n is decoded by using the header information n inserted into a predetermined position of the frame n+1.
摘要翻译：在抑制传输数据的冗余性的同时降低帧破坏的概率。在发送侧，在用于存储第n个数据的帧n中包含预定的唯一字，并且帧n之前一帧的帧n-1的帧头信息n，帧长度信息和帧头信息n-1 经过包含在帧n中的纠错编码，并发送。在接收侧，接收帧n的报头。当错误地发送帧长度信息时，通过检测下一帧n + 1中的唯一字和标题信息来指定定时。当帧n的报头未成功解码时，通过使用插入到帧n + 1的预定位置的标题信息n来解码帧n的信息数据。

3. 发明授权

US06922731B1 Gateway for reducing delay jitter and method for data transfer therein 失效
标题翻译：用于减少延迟抖动的网关及其中的数据传输方法
公开(公告)号：US06922731B1
公开(公告)日：2005-07-26
申请号：US09660041
申请日：2000-09-12
申请人： Masashi Morioka , Takashi Suzuki , Toshiro Kawahara
发明人： Masashi Morioka , Takashi Suzuki , Toshiro Kawahara
IPC分类号： H04L12/64 , H04L29/06 , H04N7/24 , H04N7/52 , G06F15/16
CPC分类号： H04L65/104 , H04L12/6418 , H04L29/06027 , H04L65/103 , H04L65/80 , H04N21/23406 , H04N21/2368 , H04N21/242 , H04N21/64707
摘要： A gateway for interconnecting two networks, comprising a receiver, a controller, and a transmitter. The receiver receives from a first network a plurality of data units in all least one form. The controller temporarily stores the data units received by the receiver and outputs the data units on the basis of the dejitterizing capability of a destination terminal served by a second network, thereby reducing jitter among delays of the data units. The transmitter sends data units corresponding to the data units output by the controller to the destination terminal through the second network.
摘要翻译：用于互连两个网络的网关，包括接收机，控制器和发射机。所述接收机以所有至少一种形式从第一网络接收多个数据单元。控制器临时存储由接收机接收的数据单元，并且基于由第二网络服务的目的地终端的去抖动能力输出数据单元，从而减少数据单元的延迟之间的抖动。发射机通过第二网络将与控制器输出的数据单元对应的数据单元发送到目的终端。

4. 发明授权

US07242718B2 Coding standard selecting method and terminal device 有权
标题翻译：编码标准选择方法和终端设备
公开(公告)号：US07242718B2
公开(公告)日：2007-07-10
申请号：US10474348
申请日：2002-09-03
申请人： Nobuhiko Naka , Takashi Suzuki
发明人： Nobuhiko Naka , Takashi Suzuki
IPC分类号： H04B14/04
CPC分类号： H04B14/04 , B32B7/02 , B32B27/06 , B32B27/18 , G02B1/116
摘要： A coding standard selecting method for selecting a coding standard used for communications between a first terminal and a second terminal, each terminal supporting multiple coding standards, is disclosed. The first terminal transmits a first signal representing all the coding standards supported by the first terminal itself to the second terminal. The second terminal selects a set of coding standards that satisfies a predetermined condition from among the coding standards represented by the first signal and among the coding standards supported by the second terminal itself, and transmits a second signal representing the selected set of coding standards to the first terminal. The first terminal selects a coding standard to be used for communication with the second terminal from the set of coding standards represented by the second signal, and transmits a third signal representing the selected coding standard to the second terminal.
摘要翻译：公开了一种用于选择用于第一终端和第二终端之间的通信的编码标准的编码标准选择方法，每个终端支持多种编码标准。第一终端将表示由第一终端本身支持的所有编码标准的第一信号发送到第二终端。第二终端从由第一信号表示的编码标准和由第二终端本身支持的编码标准中选择满足预定条件的一组编码标准，并将表示所选择的一组编码标准的第二信号发送到第一个终端。第一终端从由第二信号表示的编码标准的集合中选择要用于与第二终端的通信的编码标准，并将表示所选择的编码标准的第三信号发送到第二终端。

5. 发明授权

US07469365B2 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US07469365B2
公开(公告)日：2008-12-23
申请号：US11541228
申请日：2006-09-29
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： G06F11/00 , G06F12/16
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写入地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的比特序列的位和对应于数据D的比特序列到写入地址提供部分210中。读取地址提供部分 230交替地向操作存储器220提供用于从操作存储器220读取对应于头部H的多个连续位的多个地址和用于从操作存储器220读取对应于数据D的1位的地址，并且读取比特序列使得形成对应于标题H的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列内。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

6. 发明申请

US20050005223A1 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US20050005223A1
公开(公告)日：2005-01-06
申请号：US10885992
申请日：2004-07-06
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： H03M13/00 , H03M13/27 , H03M13/35 , H04L1/00 , H04N19/895
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写入地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的比特序列的位和对应于数据D的比特序列到写入地址提供部分210中。读取地址提供部分 230交替地向操作存储器220提供用于从操作存储器220读取对应于头部H的多个连续位的多个地址和用于从操作存储器220读取对应于数据D的1位的地址，并且读取比特序列使得形成对应于标题H的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列内。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

7. 发明授权

US07428667B2 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US07428667B2
公开(公告)日：2008-09-23
申请号：US11540059
申请日：2006-09-29
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： G06F11/00
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的位序列的位和与数据D对应的位序列的位写入到操作存储器220中。读取地址提供部件230从操作存储器220交替地向操作存储器220提供用于读取对应于头部H的多个连续位的多个地址，以及从操作中读取与数据D对应的1位的地址存储器220，并且读取比特序列，使得形成与头部H相对应的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列中。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

8. 发明授权

US06202188B1 Data transmission device 失效
标题翻译：数据传输设备
公开(公告)号：US06202188B1
公开(公告)日：2001-03-13
申请号：US08887410
申请日：1997-07-02
申请人： Takashi Suzuki , Toshio Miki , Tomoyuki Ohya , Toshiro Kawahara , Satoru Adachi
发明人： Takashi Suzuki , Toshio Miki , Tomoyuki Ohya , Toshiro Kawahara , Satoru Adachi
IPC分类号： H03M1329
CPC分类号： H04L1/0059 , H03M13/35 , H04L1/0068 , H04L2001/0098
摘要： A data transmission device comprises a transmitter device and a receiver device. The transmitter device divides a data string to be transmitted into an original data string requiring protection against code error and a data string requiring no protection. The transmitter device then carries out an error detection code adding operation and error correction coding at a redundancy code rate of 1/N on the original data string to generate a coded data string. The transmitter device divides the coded data string by N, and outputs the N divided coded data strings and the data string requiring no protection on a communication line under a time division multiplexing control. The receiver device receives the N coded data strings and the data string requiring no protection. The receiver device carries out error correction decoding on the N divided coded data strings and a mixed coded data string obtained by mixing the divided coded data strings, and carries out error detection on decoded data strings obtained by the decoding. The receiver device then outputs one of the decoded data strings from which no code error is detected together with the data string requiring no protection. The data transmission device can carry out a data transmission protecting the transmitted data from burst code errors and random code errors without increase of redundancy.
摘要翻译：数据传输设备包括发射机设备和接收机设备。发射机设备将要发送的数据串划分成需要防止代码错误的原始数据串和不需要保护的数据串。然后，发送装置在原始数据串上以1 / N的冗余码率执行错误检测码相加运算和纠错编码，生成编码数据串。发送装置将编码数据串除以N，并且在时分复用控制下，在通信线路上输出N个分割编码数据串和不需要保护的数据串。接收机设备接收N个编码数据串和不需要保护的数据串。接收机装置对N个分割编码数据串进行纠错解码，并对通过混合分割的编码数据串获得的混合编码数据串进行纠错解码，并对通过解码获得的解码数据串执行错误检测。然后，接收机装置输出检测出无代码错误的解码数据串中的一个以及不需要保护的数据串。数据传输设备可以执行保护传输数据的数据传输不受突发码错误和随机码错误的影响，而不增加冗余。

9. 发明申请

US20070038903A1 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US20070038903A1
公开(公告)日：2007-02-15
申请号：US11541228
申请日：2006-09-29
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： G06F11/00
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of-continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的位序列的位和与数据D对应的位序列的位写入到操作存储器220中。读取地址提供部件230向操作存储器220交替地提供用于从操作存储器220读取与头部H相对应的多个连续位的多个地址，以及从该存储器220读取对应于数据D的1位的地址操作存储器220，并且读取比特序列，使得形成与头部H相对应的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列中。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

10. 发明申请

US20070038902A1 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US20070038902A1
公开(公告)日：2007-02-15
申请号：US11540059
申请日：2006-09-29
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： G06F11/00
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写入地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的比特序列的位和对应于数据D的比特序列到写入地址提供部分210中。读取地址提供部分 230交替地向操作存储器220提供用于从操作存储器220读取对应于头部H的多个连续位的多个地址和用于从操作存储器220读取对应于数据D的1位的地址，并且读取比特序列使得形成对应于标题H的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列内。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

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