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1. 发明授权

US08295123B2 Current rectifying element, memory device incorporating current rectifying element, and fabrication method thereof 有权
标题翻译：电流整流元件，并联电流整流元件的存储器件及其制造方法
公开(公告)号：US08295123B2
公开(公告)日：2012-10-23
申请号：US12669174
申请日：2008-07-11
申请人： Takeshi Takagi , Takumi Mikawa , Koji Arita , Mitsuteru Iijima , Takashi Okada
发明人： Takeshi Takagi , Takumi Mikawa , Koji Arita , Mitsuteru Iijima , Takashi Okada
IPC分类号： G11C13/00
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/24 , H01L45/00
摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1
摘要翻译：在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

2. 发明申请

US20110002155A1 CURRENT CONTROL ELEMENT, MEMORY ELEMENT, AND FABRICATION METHOD THEREOF 有权
标题翻译：电流控制元件，存储器元件及其制造方法
公开(公告)号：US20110002155A1
公开(公告)日：2011-01-06
申请号：US12677413
申请日：2009-05-01
申请人： Koji Arita , Takumi Mikawa , Mitsuteru Iijima , Takashi Okada
发明人： Koji Arita , Takumi Mikawa , Mitsuteru Iijima , Takashi Okada
IPC分类号： G11C11/00 , H01L29/47 , H01L21/02
CPC分类号： H01L27/101 , H01L27/24 , H01L45/00
摘要： A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling a current flowing when the electrical pulse is applied to the resistance variable element (1); wherein the current control element (2) includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiNx, and at least one of the first electrode and the second electrode comprises α-tungsten.
摘要翻译：一种存储元件（3），其以矩阵形式布置在存储器件中，并且包括响应于施加到其上的正或负电脉冲而切换其电阻值的电阻可变元件（1），并保持所述开关电阻值; 以及电流控制元件（2），用于控制当电脉冲施加到电阻可变元件（1）时流动的电流; 其中所述电流控制元件（2）包括第一电极; 第二电极; 以及夹在所述第一电极和所述第二电极之间的电流控制层; 并且其中所述电流控制层包括SiN x，并且所述第一电极和所述第二电极中的至少一个包括α-钨。

3. 发明授权

US08422268B2 Current control element, memory element, and fabrication method thereof 有权
标题翻译：电流控制元件，存储元件及其制造方法
公开(公告)号：US08422268B2
公开(公告)日：2013-04-16
申请号：US12677413
申请日：2009-05-01
申请人： Koji Arita , Takumi Mikawa , Mitsuteru Iijima , Takashi Okada
发明人： Koji Arita , Takumi Mikawa , Mitsuteru Iijima , Takashi Okada
IPC分类号： G11C11/34 , G11C11/36 , H01L29/12
CPC分类号： H01L27/101 , H01L27/24 , H01L45/00
摘要： A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling a current flowing when the electrical pulse is applied to the resistance variable element (1); wherein the current control element (2) includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiNx, and at least one of the first electrode and the second electrode comprises α-tungsten.
摘要翻译：一种存储元件（3），其以矩阵形式布置在存储器件中，并且包括响应于施加到其上的正或负电脉冲而切换其电阻值的电阻可变元件（1），并保持所述开关电阻值; 以及电流控制元件（2），用于控制当电脉冲施加到电阻可变元件（1）时流动的电流; 其中所述电流控制元件（2）包括第一电极; 第二电极; 以及夹在所述第一电极和所述第二电极之间的电流控制层; 并且其中所述电流控制层包括SiN x，并且所述第一电极和所述第二电极中的至少一个包括α-钨。

4. 发明授权

US08351244B2 Memory cell array, nonvolatile storage device, memory cell, and method of manufacturing memory cell array 有权
标题翻译：存储单元阵列，非易失性存储设备，存储单元以及制造存储单元阵列的方法
公开(公告)号：US08351244B2
公开(公告)日：2013-01-08
申请号：US13001695
申请日：2010-05-28
申请人： Takashi Okada , Takumi Mikawa , Koji Arita
发明人： Takashi Okada , Takumi Mikawa , Koji Arita
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , H01L27/2418 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A method of manufacturing a memory cell array in which first conductive layers (2) and second conductive layers (14) extend above a semiconductor substrate (1) and three-dimensionally cross with each other, and memory cells each of which includes a current steering element (10) and a variable resistance element (23) electrically connected in series to each other is provided at a corresponding one of three-dimensional cross points between the first conductive layers (2) and the second conductive layers (14). The method includes: forming a first interlayer insulating film (3); forming a contact hole in the interlayer insulating film (3); depositing a first plug material (4) in the contact hole and on the first interlayer insulating film (3); performing a first polishing in which the first plug material (4) is polished until the first interlayer insulating film (3) is exposed; depositing a conductive film (6a) that becomes a first electrode (6) of the current steering element (10), on the first plug material (4) and the first interlayer insulating film (3) after the first polishing; and performing a second polishing in which a surface of the conductive film (6a) is polished.
摘要翻译：一种制造存储单元阵列的方法，其中第一导电层（2）和第二导电层（14）在半导体衬底（1）上方延伸并且彼此三维交叉，并且每个存储单元包括电流转向在第一导电层（2）和第二导电层（14）之间的三维交叉点中的相应一个处提供元件（10）和彼此串联电连接的可变电阻元件（23）。该方法包括：形成第一层间绝缘膜（3）; 在层间绝缘膜（3）中形成接触孔; 在所述接触孔和所述第一层间绝缘膜（3）上沉积第一插塞材料（4）; 执行抛光所述第一插塞材料（4）直到所述第一层间绝缘膜（3）露出的第一抛光; 在第一次抛光之后，在第一插头材料（4）和第一层间绝缘膜（3）上沉积成为当前操舵元件（10）的第一电极（6）的导电膜（6a）并进行抛光导电膜（6a）的表面的第二研磨。

5. 发明申请

US20110103133A1 MEMORY CELL ARRAY, NONVOLATILE STORAGE DEVICE, MEMORY CELL, AND METHOD OF MANUFACTURING MEMORY CELL ARRAY 有权
标题翻译：存储单元阵列，非易失存储器件，存储器单元及其制造存储器单元阵列的方法
公开(公告)号：US20110103133A1
公开(公告)日：2011-05-05
申请号：US13001695
申请日：2010-05-28
申请人： Takashi Okada , Takumi Mikawa , Koji Arita
发明人： Takashi Okada , Takumi Mikawa , Koji Arita
IPC分类号： G11C11/00 , H01L45/00 , H01L21/02
CPC分类号： H01L27/101 , H01L27/2418 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A method of manufacturing a memory cell array in which first conductive layers (2) and second conductive layers (14) extend above a semiconductor substrate (1) and three-dimensionally cross with each other, and memory cells each of which includes a current steering element (10) and a variable resistance element (23) electrically connected in series to each other is provided at a corresponding one of three-dimensional cross points between the first conductive layers (2) and the second conductive layers (14). The method includes: forming a first interlayer insulating film (3); forming a contact hole in the interlayer insulating film (3); depositing a first plug material (4) in the contact hole and on the first interlayer insulating film (3); performing a first polishing in which the first plug material (4) is polished until the first interlayer insulating film (3) is exposed; depositing a conductive film (6a) that becomes a first electrode (6) of the current steering element (10), on the first plug material (4) and the first interlayer insulating film (3) after the first polishing; and performing a second polishing in which a surface of the conductive film (6a) is polished.
摘要翻译：一种制造存储单元阵列的方法，其中第一导电层（2）和第二导电层（14）在半导体衬底（1）上方延伸并且彼此三维交叉，并且每个存储单元包括电流转向在第一导电层（2）和第二导电层（14）之间的三维交叉点中的相应一个处提供元件（10）和彼此串联电连接的可变电阻元件（23）。该方法包括：形成第一层间绝缘膜（3）; 在层间绝缘膜（3）中形成接触孔; 在所述接触孔和所述第一层间绝缘膜（3）上沉积第一插塞材料（4）; 执行抛光所述第一插塞材料（4）直到所述第一层间绝缘膜（3）露出的第一抛光; 在第一次抛光之后，在第一插头材料（4）和第一层间绝缘膜（3）上沉积成为当前操舵元件（10）的第一电极（6）的导电膜（6a）并进行抛光导电膜（6a）的表面的第二研磨。

6. 发明申请

US20100193760A1 CURRENT RESTRICTING ELEMENT, MEMORY APPARATUS INCORPORATING CURRENT RESTRICTING ELEMENT, AND FABRICATION METHOD THEREOF 有权
标题翻译：电流限制元件，包含电流限制元件的记忆装置及其制造方法
公开(公告)号：US20100193760A1
公开(公告)日：2010-08-05
申请号：US12669174
申请日：2008-07-11
申请人： Takeshi Takagi , Takumi Mikawa , Koji Arita , Mitsuteru Iijima , Takashi Okada
发明人： Takeshi Takagi , Takumi Mikawa , Koji Arita , Mitsuteru Iijima , Takashi Okada
IPC分类号： H01L45/00 , H01L27/04 , H01L21/02
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/24 , H01L45/00
摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1
摘要翻译：在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

7. 发明授权

US08537605B2 Nonvolatile semiconductor memory device having coplanar surfaces at resistance variable layer and wiring layer and manufacturing method thereof 有权
标题翻译：在电阻变化层和布线层具有共面的非易失性半导体存储器件及其制造方法
公开(公告)号：US08537605B2
公开(公告)日：2013-09-17
申请号：US12867437
申请日：2009-02-09
申请人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
发明人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
IPC分类号： G11C11/14
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.
摘要翻译：非易失性半导体存储器件（100）包括设置有晶体管（101）的衬底（102）; 形成在所述衬底上以覆盖所述晶体管的第一层间绝缘层（103）形成在所述第一层间绝缘层中并电连接到所述晶体管的漏电极（101a）或源电极（101b）中的任一个的第一接触插塞（104）和形成在所述第一中间层绝缘层并与晶体管的漏电极或源电极中的另一个电连接; 形成为覆盖所述第一接触插塞的一部分的电阻变化层（106）形成在电阻变化层上的第一线（107）以及形成为覆盖所述第二接触插塞的一部分的第二线（108）所述电阻变化层的端面与所述第一线的端面共面。

8. 发明申请

US20130171799A1 CURRENT STEERING ELEMENT AND NON-VOLATILE MEMORY ELEMENT INCORPORATING CURRENT STEERING ELEMENT 有权
标题翻译：电流转向元件和非易失性存储元件包含电流转向元件
公开(公告)号：US20130171799A1
公开(公告)日：2013-07-04
申请号：US13823667
申请日：2011-09-16
申请人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
发明人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
IPC分类号： H01L45/00 , H01L21/768
CPC分类号： H01L45/16 , H01L21/768 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L45/00 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.
摘要翻译：一种形成为当前的操舵元件覆盖形成在层间绝缘层（102）中的通孔（104）的下开口（105）的电流控制元件（100），包括：形成在通孔的下开口的下侧，使得防蚀层覆盖下开口的整个部分; 形成在所述腐蚀抑制层下方并且包含不同于所述腐蚀抑制层的材料的材料的第二电极层（108）形成在所述第二电极层下方的电流转向层（110），使得所述电流导向层物理地与所述第二电极层接触; 以及第一电极层（112），形成在所述电流导向层下方，使得所述第一电极层物理地与所述电流转向层接触; 并且第一电极层，电流导向层和第二电极层构成MSM二极管和MIM二极管之一。

9. 发明申请

US20110220862A1 RESISTANCE VARIABLE ELEMENT AND RESISTANCE VARIABLE MEMORY DEVICE 有权
标题翻译：电阻可变元件和电阻可变存储器件
公开(公告)号：US20110220862A1
公开(公告)日：2011-09-15
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

10. 发明授权

US08759190B2 Current steering element and non-volatile memory element incorporating current steering element 有权
标题翻译：目前的导向元件和非易失性存储元件结合了当前的转向元件
公开(公告)号：US08759190B2
公开(公告)日：2014-06-24
申请号：US13823667
申请日：2011-09-16
申请人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
发明人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
IPC分类号： H01L21/20
CPC分类号： H01L45/16 , H01L21/768 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L45/00 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.
摘要翻译：一种形成为当前的操舵元件覆盖形成在层间绝缘层（102）中的通孔（104）的下开口（105）的电流控制元件（100），包括：形成在通孔的下开口的下侧，使得防蚀层覆盖下开口的整个部分; 形成在所述腐蚀抑制层下方并且包含不同于所述腐蚀抑制层的材料的材料的第二电极层（108）形成在所述第二电极层下方的电流转向层（110），使得所述电流导向层物理地与所述第二电极层接触; 以及第一电极层（112），形成在所述电流导向层下方，使得所述第一电极层物理地与所述电流转向层接触; 并且第一电极层，电流导向层和第二电极层构成MSM二极管和MIM二极管之一。

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