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1. 发明授权

US5973359A MOS type semiconductor device 有权
标题翻译： MOS型半导体器件
公开(公告)号：US5973359A
公开(公告)日：1999-10-26
申请号：US190929
申请日：1998-11-12
申请人： Takashi Kobayashi , Tatsuhiko Fujihira , Shigeyuki Takeuchi , Yoshiki Kondo , Shoichi Furuhata
发明人： Takashi Kobayashi , Tatsuhiko Fujihira , Shigeyuki Takeuchi , Yoshiki Kondo , Shoichi Furuhata
IPC分类号： H01L29/739 , H01L21/76 , H01L27/02 , H01L27/04 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/7395 , H01L27/0251 , H01L27/0255 , H01L29/1095 , H01L29/7808 , H01L29/7811
摘要： A MOS type semiconductor device is provided which includes a series Zener diode array for overvoltage protection, which is provided between source regions and an electrode having substantially the same potential as a drain electrode, and a field insulating film on which the series Zener diode array is provided. The thickness T (.mu.m) of the field insulating film is determined as a function of the clamp voltage V.sub.CE (V) of the series Zener diode array, such that the thickness T is held in the range as represented by: T.gtoreq.2.0.times.10.sup.-3 .times.V.sub.CE. The width W.sub.1 (.mu.m) of a portion of a second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is provided, and the width W.sub.2 (.mu.m) of a portion of the second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is not provided, are determined as a function of the clamp voltage V.sub.CE of the series Zener diode array, such that the widths W.sub.1, W.sub.2 are held in respective ranges as represented by: W.sub.1 .gtoreq.0.15 V.sub.CE, and W.sub.2 .gtoreq.0.05 V.sub.CE. By controlling the widths W.sub.1, W.sub.2 to these ranges, respectively, the concentration of current into an end portion of the cell portion of the device can be prevented upon cut-off of current from an inductive load.
摘要翻译：提供一种MOS型半导体器件，其包括用于过电压保护的串联齐纳二极管阵列，其设置在源极区域和具有与漏极电极基本相同的电位的电极之间，以及场致绝缘膜，串联齐纳二极管阵列提供。确定场绝缘膜的厚度T（μm）作为串联齐纳二极管阵列的钳位电压VCE（V）的函数，使得厚度T保持在如下所示的范围内：T> / = 2.0x10-3xVCE。第二导电型隔离阱的与串联齐纳二极管阵列的场绝缘膜接近的部分的宽度W1（μm）和宽度W2（μm）靠近不具有串联齐纳二极管阵列的场绝缘膜的第二导电型隔离阱被确定为串联齐纳二极管阵列的钳位电压VCE的函数，使得宽度W1，W2 保持在各自的范围内，如：W1> / = 0.15VCE，W2> / = 0.05VCE。通过分别将宽度W1，W2控制到这些范围，可以在从感性负载切断电流时，防止电流进入器件的电池部分端部的电流的浓度。

2. 发明授权

US06462382B2 MOS type semiconductor apparatus 有权
标题翻译： MOS型半导体装置
公开(公告)号：US06462382B2
公开(公告)日：2002-10-08
申请号：US09811736
申请日：2001-03-19
申请人： Kazuhiko Yoshida , Tatsuhiko Fujihira , Motoi Kudoh , Shoichi Furuhata , Shigeyuki Takeuchi
发明人： Kazuhiko Yoshida , Tatsuhiko Fujihira , Motoi Kudoh , Shoichi Furuhata , Shigeyuki Takeuchi
IPC分类号： H01L2362
CPC分类号： H01L29/7395 , H01L25/071 , H01L27/0255 , H01L27/0635 , H01L29/1095 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.
摘要翻译：提供一种MOS型半导体装置，其包括主MOS型半导体器件，连接在控制输入端子（G）和主MOS型半导体器件的控制输入端口（g）之间的内部控制电路以及连接的保护器件控制输入端子（G）和设备的输出端子（S）之一，用于保护半导体器件或内部控制电路免受过电压。保护装置包括：第一分支，包括由在半导体衬底上沉积在绝缘膜上的多晶硅层组成的齐纳二极管（Z1p）;以及包括形成在半导体衬底的表面层中的齐纳二极管（Z21）的第二支路，以及二极管（Z3pr），其由沉积在半导体衬底上的绝缘膜上的多晶硅层构成，并且与齐纳二极管（Z21）反向连接。第一和第二分支彼此并联连接。

3. 发明授权

US06229180B1 MOS type semiconductor apparatus 有权
公开(公告)号：US06229180B1
公开(公告)日：2001-05-08
申请号：US09238855
申请日：1999-01-27
申请人： Kazuhiko Yoshida , Tatsuhiko Fujihira , Motoi Kudoh , Shoichi Furuhata , Shigeyuki Takeuchi
发明人： Kazuhiko Yoshida , Tatsuhiko Fujihira , Motoi Kudoh , Shoichi Furuhata , Shigeyuki Takeuchi
IPC分类号： H01L2362
CPC分类号： H01L29/7395 , H01L25/071 , H01L27/0255 , H01L27/0635 , H01L29/1095 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.

4. 发明授权

US5970964A Circuit device for igniting internal combustion engine and semiconductor device for igniting internal combustion engine 失效
标题翻译：用于点燃内燃机的电路装置和用于点燃内燃机的半导体装置
公开(公告)号：US5970964A
公开(公告)日：1999-10-26
申请号：US768360
申请日：1996-12-17
申请人： Shoichi Furuhata , Shigeyuki Takeuchi , Tatsuhiko Fujihira
发明人： Shoichi Furuhata , Shigeyuki Takeuchi , Tatsuhiko Fujihira
IPC分类号： F02P3/05 , F02P3/055
CPC分类号： F02P3/051 , F02P3/0552
摘要： A circuit is provided in which a voltage due to a minute current is applied to a gate terminal from a collector terminal when a collector voltage is higher than a gate voltage in an operation of current limitation. Thus, an increase in the collector voltage immediately after the operation of current limitation starts serves to boost the gate voltage. The boosted voltage suppress an abrupt increase in the collector voltage. When the collector voltage is reduced by oscillation, the action of boosting the gate voltage is lowered to suppress the reduction of the collector voltage.
摘要翻译：提供一种电路，其中当电流限制的操作中集电极电压高于栅极电压时，由微小电流引起的电压从集电极端子施加到栅极端子。因此，在电流限制开始运行之后立即增加集电极电压来提高栅极电压。升压电压抑制集电极电压的突然增加。当通过振荡减小集电极电压时，降低栅极电压升压的作用以抑制集电极电压的降低。

5. 发明授权

US5621601A Over-current protection apparatus for transistor 失效
标题翻译：晶体管过电流保护装置
公开(公告)号：US5621601A
公开(公告)日：1997-04-15
申请号：US314320
申请日：1994-09-28
申请人： Tatsuhiko Fujihira , Shin Kiuchi , Kazuhiko Yoshida , Yukio Yano , Kazunori Oyabe , Shoichi Furuhata , Tetsuhiro Morimoto
发明人： Tatsuhiko Fujihira , Shin Kiuchi , Kazuhiko Yoshida , Yukio Yano , Kazunori Oyabe , Shoichi Furuhata , Tetsuhiro Morimoto
IPC分类号： H01L29/78 , G05F1/56 , H01L27/02 , H01L27/04 , H02H7/12 , H02M1/00 , H03K17/082 , H02H3/00
CPC分类号： H03K17/0822 , H01L27/0248 , H03F1/52 , H03K17/0828
摘要： The disclosed invention is designed to prevent the oscillation which often occurs in an over-current protection apparatus for an insulated gate controlled transistor. The apparatus improves the response in current detection, to prevent oscillation, and improves protection speed against over-current. This is accomplished by separating the gates of the main transistor and the current detector transistor; by setting a shorter time constant for the gate circuit of the current detector transistor than that of the gate circuit of the main transistor; by feeding the detection signal obtained from the current detecting means which detects the current i of the current detector transistor proportional to the current I flowing through the main transistor, to the control means; and by controlling the gate potentials of both transistors to protect the main transistor from the over-current by feeding the comparison output Sd from the comparator circuit, which compares the voltage of the signal Vd with the reference voltage Vr, to the control circuit.
摘要翻译：所公开的发明被设计为防止在绝缘栅极控制晶体管的过电流保护装置中经常发生的振荡。该装置提高了电流检测中的响应，防止振荡，提高了防过电流的保护速度。这通过分离主晶体管和电流检测器晶体管的栅极来实现; 通过为电流检测器晶体管的栅极电路设置比主晶体管的栅极电路的时间常数更短的时间常数; 通过将检测到与流过主晶体管的电流I成比例的电流检测器晶体管的电流i的电流检测装置获得的检测信号馈送到控制装置; 并且通过控制两个晶体管的栅极电位，通过将比较电路的比较输出Sd与信号Vd与参考电压Vr进行比较来控制主晶体管的过电流来保护主晶体管。

6. 发明授权

US5202619A Control circuit for a switching transistor 失效
标题翻译：开关晶体管的控制电路
公开(公告)号：US5202619A
公开(公告)日：1993-04-13
申请号：US751932
申请日：1991-08-30
申请人： Shoichi Furuhata , Naoto Fujisawa , Seiki Igarashi
发明人： Shoichi Furuhata , Naoto Fujisawa , Seiki Igarashi
IPC分类号： H03K17/0412 , H03K17/64
CPC分类号： H03K17/64 , H03K17/04126
摘要： In a switching transistor control circuit, the switching transistor has a control electrode and first and second main circuit electrodes. A reactor is connected in series with the first main circuit electrode of the switching transistor to receive a main circuit current through the switching transistor. Circuitry is connected to an end of the reactor remote from the first main electrode and to the control electrode of the switching transistor, for supplying an electromotive force to the control electrode which is generated by the reactor as main circuit current decreases when the switching transistor is turned off. A control electrode driving circuit is connected to the control electrode, and is connected to one of the first main circuit electrode and a predetermined intermediate position on the reactor, for supplying a drive signal to the control electrode for selectively turning the switching transistor on and off.
摘要翻译：在开关晶体管控制电路中，开关晶体管具有控制电极和第一和第二主电路电极。电抗器与开关晶体管的第一主电路电极串联连接，以接收通过开关晶体管的主电路电流。电路连接到远离第一主电极和开关晶体管的控制电极的反应堆的端部，用于当开关晶体管为主电路电流时主电路电流减小时，向由电抗器产生的控制电极提供电动势关掉。控制电极驱动电路连接到控制电极，并且连接到电抗器上的第一主电路电极和预定中间位置之一，用于向控制电极提供驱动信号，用于选择性地使开关晶体管接通和断开。

7. 发明授权

US5091664A Insulated gate bipolar transistor circuit with overcurrent protection 失效
标题翻译：绝缘栅双极晶体管电路，具有过流保护功能
公开(公告)号：US5091664A
公开(公告)日：1992-02-25
申请号：US482896
申请日：1990-02-22
申请人： Shoichi Furuhata
发明人： Shoichi Furuhata
IPC分类号： H02M7/537 , H03K17/08 , H03K17/082
CPC分类号： H03K17/0828
摘要： A semiconductive device integrated on a single chip and adapted for self-protecting use in control applications, including an insulated gate bipolar transistor (IGBT) useful as a series controller for a load. In the event of a load failure (short), the upward current excursion is inhibited by a control arrangement in which a sensing resistor in the emitter circuit of the IGBT turns on a three-terminal signal shunt across the signal control path of the IGBT. The signal shunt includes a voltage dropping element such as a Zener diode and may also include Zener reverse-voltage protection. The sensing resistor may be placed in the low-current branch of a split-emitter current path of the IGBT. A pulsed constant-amplitude driving signal may be applied to the control signal path of the IGBT through serially-connected NPN and PNP bipolar transistors providing a common driving node connected through a serial impedance to the control signal path of the IGBT and to the signal shunt.
摘要翻译：集成在单个芯片上并适用于控制应用中的自我保护的半导体器件，包括用作负载的串联控制器的绝缘栅双极晶体管（IGBT）。在负载故障（短路）的情况下，通过IGBT的发射电路中的感测电阻器在IGBT的信号控制路径上的三端信号分流的控制装置阻止向上电流偏移。信号分流器包括诸如齐纳二极管的降压元件，并且还可以包括齐纳反向电压保护。感测电阻可以放置在IGBT的分流 - 发射极电流路径的低电流分支中。脉冲恒幅驱动信号可以通过串联NPN和PNP双极晶体管施加到IGBT的控制信号路径，NPN和PNP双极晶体管提供通过串联阻抗连接到IGBT的控制信号路径的公共驱动节点和信号分流。

8. 发明授权

US4825279A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4825279A
公开(公告)日：1989-04-25
申请号：US104083
申请日：1987-10-05
申请人： Shoichi Furuhata
发明人： Shoichi Furuhata
IPC分类号： H01L29/73 , H01L21/331 , H01L21/60 , H01L23/495 , H01L25/04 , H01L25/07 , H01L25/18 , H01L23/48 , H01L23/16 , H01L29/44 , H01L29/46
CPC分类号： H01L23/49575 , H01L24/49 , H01L25/072 , H01L2224/48091 , H01L2224/48092 , H01L2224/48227 , H01L2224/49 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/1301 , H01L2924/1305 , H01L2924/1306 , H01L2924/30107
摘要： In a semiconductor device made up of semiconductor elements, a plurality of terminal boards are laid one on another with insulating boards therebetween such that the terminal boards are in parallel with the semiconductor elements and are shifted from one another. The terminal boards are fixedly secured to a substrate through an insulating board, the terminal boards having upwardly extended terminals arranged in parallel and spaced slightly apart fron one another, and lead wires interconnect the electrodes of the semiconductor elements and the exposed surfaces of the terminal boards such that the lead wires extend in a direction perpendicular to the direction of arrangement of the semiconductor elements, whereby substantially equal inductances between the electrodes of the semiconductor elements and the terminals are compensated and are made small.
摘要翻译：在由半导体元件构成的半导体器件中，多个端子板彼此之间具有绝缘板，使得端子板与半导体元件并联并且彼此偏移。端子板通过绝缘板固定到基板上，端子板具有彼此平行排列并彼此间隔开的彼此间隔开的向上延伸的端子，并且引线将半导体元件的电极和端子板的暴露表面互连使得引线沿着与半导体元件的布置方向垂直的方向延伸，由此半导体元件的电极和端子之间的基本相等的电感被补偿并且被制成较小的。

9. 发明申请

US20080285188A1 Composite integrated semiconductor device 有权
标题翻译：复合集成半导体器件
公开(公告)号：US20080285188A1
公开(公告)日：2008-11-20
申请号：US12071604
申请日：2008-02-22
申请人： Shin Kiuchi , Kazuhiko Yoshida , Takeshi Ichimura , Naoki Yaezawa , Shoichi Furuhata
发明人： Shin Kiuchi , Kazuhiko Yoshida , Takeshi Ichimura , Naoki Yaezawa , Shoichi Furuhata
IPC分类号： H02H9/04
CPC分类号： H03F3/45475 , H01L23/552 , H01L27/0255 , H01L2924/0002 , H03F1/26 , H03F1/52 , H03F2200/372 , H03F2200/444 , H03F2203/45136 , H01L2924/00
摘要： A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating circuit attenuates the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.
摘要翻译：复合集成半导体器件。在一个实施例中，输入浪涌/噪声吸收电路从输入信号吸收浪涌，衰减电路衰减输入信号，电信号转换电路将输入信号转换成输出信号。输入浪涌/噪声吸收电路，衰减电路和电信号转换电路一起形成一个单元，并且多个这些单元并联在一个半导体衬底中以形成复合集成半导体器件，从而减少安装在印刷电路板上的分立组件的数量。

10. 发明申请

US20070285855A1 Composite integrated semiconductor device 有权
标题翻译：复合集成半导体器件
公开(公告)号：US20070285855A1
公开(公告)日：2007-12-13
申请号：US11723356
申请日：2007-03-19
申请人： Shin Kiuchi , Kazuhiko Yoshida , Takeshi Ichimura , Naoki Yaezawa , Shoichi Furuhata
发明人： Shin Kiuchi , Kazuhiko Yoshida , Takeshi Ichimura , Naoki Yaezawa , Shoichi Furuhata
IPC分类号： H02H9/04
CPC分类号： H03F1/52 , H01L23/552 , H01L27/0255 , H01L2924/0002 , H03F1/26 , H03F3/45475 , H03F2200/372 , H03F2200/444 , H03F2203/45136 , H01L2924/00
摘要： A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating/level-shifting circuit attenuates or level-shifts the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating or level-shifting circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.
摘要翻译：复合集成半导体器件。在一个实施例中，输入浪涌/噪声吸收电路从输入信号吸收浪涌，衰减/电平移位电路衰减或电平移位输入信号，电信号转换电路将输入信号转换为输出信号。输入浪涌/噪声吸收电路，衰减或电平移位电路和电信号转换电路一起形成一个单元，并且多个这些单元并联在一个半导体衬底中以形成复合集成半导体器件，从而得到减少安装在印刷电路板上的分立元件的数量。

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