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1. 发明授权

US07927997B2 Flip-chip mounting method and bump formation method 有权
标题翻译：倒装芯片安装方法和凸块形成方法
公开(公告)号：US07927997B2
公开(公告)日：2011-04-19
申请号：US11579299
申请日：2006-03-07
申请人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita , Seiichi Nakatani
发明人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita , Seiichi Nakatani
IPC分类号： H01L21/445
CPC分类号： H01L21/563 , B23K35/0244 , H01L21/67144 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/75 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1131 , H01L2224/13099 , H01L2224/1319 , H01L2224/133 , H01L2224/16 , H01L2224/75 , H01L2224/83192 , H01L2224/8321 , H01L2224/83815 , H01L2224/83886 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/18161 , H01L2924/30105 , H05K3/323 , H05K3/3436 , H05K3/3484 , H05K2201/10977 , H05K2203/1361 , Y02P70/613 , Y10T29/53178 , H01L2224/05599
摘要： To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability.A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.
摘要翻译：提供适用于下一代LSI的倒装安装并具有高生产率和高可靠性的倒装芯片安装方法和凸块形成方法。具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21，其间设置有给定的间隙，并且在该状态下将半导体芯片20和电路板21浸入浸渍浴40含有包含熔融的焊料颗粒的熔融树脂14一段给定的时间。在该浸渍过程中，熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间，从而在这些端子之间形成连接器22。此后，半导体芯片20和电路板21从浸渍浴40中取出，并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化，芯片安装体。

2. 发明申请

US20110049598A1 MANUFACTURING METHOD OF FLEXIBLE SEMICONDUCTOR DEVICE AND FLEXIBLE SEMICONDUCTOR DEVICE 有权
标题翻译：柔性半导体器件和柔性半导体器件的制造方法
公开(公告)号：US20110049598A1
公开(公告)日：2011-03-03
申请号：US12939729
申请日：2010-11-04
申请人： Koichi HIRANO , Seiichi Nakatani , Shingo Komatsu , Yoshihisa Yamashita , Takashi Ichiryu
发明人： Koichi HIRANO , Seiichi Nakatani , Shingo Komatsu , Yoshihisa Yamashita , Takashi Ichiryu
IPC分类号： H01L29/786
CPC分类号： H01L51/0024 , H01L29/41733 , H01L29/66742 , H01L29/78603 , H01L51/0023 , H01L51/0097 , H01L51/0525 , H01L51/055 , H01L51/102 , Y10T428/24917
摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
摘要翻译：制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

3. 发明授权

US07726545B2 Flip chip mounting process and bump-forming process using electrically-conductive particles as nuclei 有权
标题翻译：使用导电颗粒作为核的倒装芯片安装工艺和凸块形成工艺
公开(公告)号：US07726545B2
公开(公告)日：2010-06-01
申请号：US11886311
申请日：2006-03-13
申请人： Takashi Ichiryu , Seiichi Nakatani , Seiji Karashima , Yoshihiro Tomita , Koichi Hirano , Toshio Fujii
发明人： Takashi Ichiryu , Seiichi Nakatani , Seiji Karashima , Yoshihiro Tomita , Koichi Hirano , Toshio Fujii
IPC分类号： B23K31/02 , B23K31/00 , H01L21/44
CPC分类号： H05K3/3436 , H01L21/4853 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/11005 , H01L2224/1152 , H01L2224/11524 , H01L2224/16 , H01L2224/73104 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2224/83886 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K3/323 , H05K3/3484 , H05K2201/10977 , H05K2203/083 , H05K2203/087 , Y02P70/613 , Y10T29/49126 , H01L2224/13099 , H01L2224/29099 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A flip chip mounting process or a bump-forming process according to the present invention is characterized in that electrically-conductive particles are fixed on electrodes formed on an electronic component. A composition comprising solder powder, a convection additive and a resin component is supplied onto a surface of the electronic component, the surface is provided with the electrodes. The supplied composition is heated up to a temperature enabling the solder powder to melt. As a result, the convection additive boils or is decomposed so as to generate a gas. The generated gas produces a convection phenomenon within the supplied composition. Since the convection phenomenon promotes the movement of the solder powder, the solder powder can move freely within the composition. The electrically-conductive particles serve as nuclei for the solder powder to self-assemble and grow. As a result, the molten solder powder is allowed to self-assemble and grow in the vicinity of the electrically-conductive particles, which leads to a formation of connections or bumps.
摘要翻译：根据本发明的倒装芯片安装工艺或凸块形成工艺的特征在于，导电颗粒固定在形成在电子部件上的电极上。将包含焊料粉末，对流添加剂和树脂组分的组合物供应到电子部件的表面上，该表面设置有电极。将所提供的组合物加热到使焊料粉末熔化的温度。结果，对流添加剂沸腾或分解以产生气体。所产生的气体在所提供的组合物内产生对流现象。由于对流现象促使焊料粉末的移动，焊料粉末可以在组合物内自由移动。导电颗粒用作焊料粉末的自组装和生长的核。结果，允许熔融焊料粉末在导电颗粒附近自组装和生长，这导致连接或凸块的形成。

4. 发明申请

US20080165518A1 Flip Clip Mounting Process And Bump-Forming Process Using Electrically-Conductive Particles 有权
标题翻译：使用导电颗粒的翻转夹安装工艺和凸起成型工艺
公开(公告)号：US20080165518A1
公开(公告)日：2008-07-10
申请号：US11886311
申请日：2006-03-13
申请人： Takashi Ichiryu , Seiichi Nakatani , Seiji Karashima , Yoshihiro Tomita , Koichi Hirano , Toshio Fujii
发明人： Takashi Ichiryu , Seiichi Nakatani , Seiji Karashima , Yoshihiro Tomita , Koichi Hirano , Toshio Fujii
IPC分类号： H01L23/498 , H05K3/36 , B23K1/20 , H01L21/60
CPC分类号： H05K3/3436 , H01L21/4853 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/11005 , H01L2224/1152 , H01L2224/11524 , H01L2224/16 , H01L2224/73104 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2224/83886 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K3/323 , H05K3/3484 , H05K2201/10977 , H05K2203/083 , H05K2203/087 , Y02P70/613 , Y10T29/49126 , H01L2224/13099 , H01L2224/29099 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A flip chip mounting process or a bump-forming process according to the present invention is characterized in that electrically-conductive particles are fixed on electrodes formed on an electronic component. A composition comprising solder powder, a convection additive and a resin component is supplied onto a surface of the electronic component, the surface is provided with the electrodes. The supplied composition is heated up to a temperature enabling the solder powder to melt. As a result, the convection additive boils or is decomposed so as to generate a gas. The generated gas produces a convection phenomenon within the supplied composition. Since the convection phenomenon promotes the movement of the solder powder, the solder powder can move freely within the composition. The electrically-conductive particles serve as nuclei for the solder powder to self-assemble and grow. As a result, the molten solder powder is allowed to self-assemble and grow in the vicinity of the electrically-conductive particles, which leads to a formation of connections or bumps.
摘要翻译：根据本发明的倒装芯片安装工艺或凸块形成工艺的特征在于，导电颗粒固定在形成在电子部件上的电极上。将包含焊料粉末，对流添加剂和树脂组分的组合物供应到电子部件的表面上，该表面设置有电极。将所提供的组合物加热到使焊料粉末熔化的温度。结果，对流添加剂沸腾或分解以产生气体。所产生的气体在所提供的组合物内产生对流现象。由于对流现象促使焊料粉末的移动，焊料粉末可以在组合物内自由移动。导电颗粒用作焊料粉末的自组装和生长的核。结果，允许熔融焊料粉末在导电颗粒附近自组装和生长，这导致连接或凸块的形成。

5. 发明授权

US08343822B2 Flexible semiconductor device and method for manufacturing same 有权
标题翻译：柔性半导体器件及其制造方法
公开(公告)号：US08343822B2
公开(公告)日：2013-01-01
申请号：US12681445
申请日：2009-07-30
申请人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa , Takashi Ichiryu , Takeshi Suzuki
发明人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa , Takashi Ichiryu , Takeshi Suzuki
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/78651 , H01L27/1218 , H01L27/124 , H01L27/1266 , H01L29/41733 , H01L29/42384 , H01L29/78603 , H01L29/7869
摘要： A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.
摘要翻译：一种制造柔性半导体器件的方法包括：（i）在金属箔的上表面上形成绝缘膜，（ii）在金属箔的上表面上形成引出电极图案，（iii）在金属箔的上表面上形成半导体层绝缘膜，使得半导体层与引出电极图案接触，（iv）在金属箔的上表面上形成密封树脂层，使得密封树脂层覆盖半导体层和引出电极图案，和（ v）通过蚀刻金属箔形成电极，金属箔用作绝缘膜的支撑体，引出电极图案，半导体层和形成在（i）至（iv）中的密封树脂层，并用作（v）中的电极的构成材料。金属箔不需要剥离，可以使用高温工艺。

6. 发明授权

US07981528B2 Magnetic sheet with stripe-arranged magnetic grains, RFID magnetic sheet, magnetic shielding sheet and method of manufacturing the same 有权
标题翻译：具有带状磁性颗粒的磁性片，RFID磁性片，磁屏蔽片及其制造方法
公开(公告)号：US07981528B2
公开(公告)日：2011-07-19
申请号：US11848407
申请日：2007-08-31
申请人： Seiichi Nakatani , Yoshihisa Yamashita , Takashi Ichiryu , Koichi Hirano
发明人： Seiichi Nakatani , Yoshihisa Yamashita , Takashi Ichiryu , Koichi Hirano
IPC分类号： B32B15/00
CPC分类号： G06K19/07749 , G06K19/07771 , Y10T428/24355 , Y10T428/32
摘要： A water-repelling layer is formed on a resin film, and a stripe pattern region is formed so as to be positioned within a surface region of the water-repelling layer and so as to be relatively hydrophilic with respect to water repellency of the water-repelling layer. A magnetic stripe pattern is formed of needle-shaped magnetic grains oriented and aggregated in the stripe pattern region. The needle-shaped magnetic grains are arranged in a desirable state in a predetermined stripe pattern, with a high magnetic permeability and a magnetic sheet with stripe-arranged magnetic grains that is thin and flexible is obtained.
摘要翻译：在树脂膜上形成防水层，并且形成条纹图案区域，以便位于防水层的表面区域内，并且相对于水溶性防水层的防水性而相对亲水，排斥层。磁条图案由在条纹图案区域中定向和聚集的针状磁性颗粒形成。针状磁性颗粒以预定的条纹图案被布置成期望的状态，具有高磁导率，并且获得薄且柔性的带状排列的磁性颗粒的磁性片。

7. 发明申请

US20110162578A1 FLIP-CHIP MOUNTING METHOD AND BUMP FORMATION METHOD 有权
标题翻译： FLIP-CHIP安装方法和BUMP形成方法
公开(公告)号：US20110162578A1
公开(公告)日：2011-07-07
申请号：US13046151
申请日：2011-03-11
申请人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita , Seiichi Nakatani
发明人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita , Seiichi Nakatani
IPC分类号： H01L21/70 , B05C3/02 , B05C9/14 , B05C13/02 , B05C11/00 , B05C11/10 , H01L21/687
CPC分类号： H01L21/563 , B23K35/0244 , H01L21/67144 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/75 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1131 , H01L2224/13099 , H01L2224/1319 , H01L2224/133 , H01L2224/16 , H01L2224/75 , H01L2224/83192 , H01L2224/8321 , H01L2224/83815 , H01L2224/83886 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/18161 , H01L2924/30105 , H05K3/323 , H05K3/3436 , H05K3/3484 , H05K2201/10977 , H05K2203/1361 , Y02P70/613 , Y10T29/53178 , H01L2224/05599
摘要： [Problem] To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability.[Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.
摘要翻译： [问题]提供一种适用于下一代LSI的倒装安装并具有高生产率和高可靠性的倒装芯片安装方法和凸块形成方法。解决问题的手段具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21，其间设置有给定的间隙，半导体芯片20和电路板21 将该状态浸渍在包含熔融的焊料颗粒的熔融树脂14的浸渍浴40中一段给定的时间。在该浸渍过程中，熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间，从而在这些端子之间形成连接器22。此后，半导体芯片20和电路板21从浸渍浴40中取出，并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化，芯片安装体。

8. 发明申请

US20110121298A1 MANUFACTURING METHOD OF FLEXIBLE SEMICONDUCTOR DEVICE 有权
标题翻译：柔性半导体器件的制造方法
公开(公告)号：US20110121298A1
公开(公告)日：2011-05-26
申请号：US13054049
申请日：2010-02-05
申请人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
发明人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78603 , H01L27/1218 , H01L27/1266 , H01L29/458 , H01L29/4908 , H01L29/78681 , H01L29/7869 , H01L2224/24195 , H01L2224/32245 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2924/3511 , H01L2924/3512
摘要： A method includes the steps of preparing a multilayer film 80 formed by sequentially stacking a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40; forming a source electrode 42s and a drain electrode 42d comprised of the second metal layer 40 by etching the second metal layer 40; pressure-bonding a resin layer 50 onto a surface of the multilayer film 80 provided with the source electrode 42s and the drain electrode 42d to burry the source electrode 42s and the drain electrode 42d in the resin layer 50; and forming a gate electrode 10g comprised of the first metal layer 10 by etching the first metal layer 10. The inorganic insulating layer 20g functions as a gate insulating film. The semiconductor layer 30 functions as a channel.
摘要翻译：一种方法包括制备通过顺序堆叠第一金属层10，无机绝缘层20，半导体层30和第二金属层40而形成的多层膜80的步骤; 通过蚀刻第二金属层40形成由第二金属层40构成的源电极42s和漏电极42d; 将树脂层50压接到设置有源电极42s和漏电极42d的多层膜80的表面，以将树脂层50中的源电极42s和漏电极42d嵌入; 以及通过蚀刻第一金属层10形成由第一金属层10构成的栅极电极10g。无机绝缘层20g用作栅极绝缘膜。半导体层30用作沟道。

9. 发明申请

US20050184381A1 Connection member and mount assembly and production method of the same 有权
标题翻译：连接构件和安装组装及生产方法相同
公开(公告)号：US20050184381A1
公开(公告)日：2005-08-25
申请号：US11060550
申请日：2005-02-18
申请人： Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
发明人： Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
IPC分类号： H01R13/24 , H05K1/00 , H05K1/02 , H05K1/14 , H05K1/18 , H05K3/20 , H05K3/34 , H05K3/36 , H05K3/40 , H01R27/02 , H01L23/48 , H01R12/00 , H01R25/00 , H01R31/00 , H01R33/88 , H01R33/90 , H01R33/92 , H01R33/94
CPC分类号： H05K3/403 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H01R13/2414 , H05K1/0218 , H05K1/0284 , H05K1/141 , H05K1/145 , H05K1/182 , H05K3/20 , H05K3/3442 , H05K3/361 , H05K3/366 , H05K3/368 , H05K2201/043 , H05K2201/048 , H05K2201/049 , H05K2201/055 , H05K2201/056 , H05K2201/09036 , H05K2201/10515 , H05K2201/10689 , H05K2203/302 , Y10T29/49117 , Y10T29/49126 , Y10T29/49208 , H01L2924/00
摘要： A connection member is provided which can be produced without a via-forming step. The connection member 100 includes an insulating substrate 10 which has an upper surface 10a, a lower surface 10b opposed to the upper surface 10b and a side surface 10c which connects these surfaces; at least one wiring 20 which extends from the upper surface to the lower surface through the side surface.
摘要翻译：提供了可以在没有通孔形成步骤的情况下制造的连接构件。连接构件100包括绝缘基板10，其具有上表面10a，与上表面10b相对的下表面10b和连接这些表面的侧表面10c; 至少一个布线20，其通过侧表面从上表面延伸到下表面。

10. 发明申请

US20120181543A1 FLEXIBLE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：柔性半导体器件及其制造方法
公开(公告)号：US20120181543A1
公开(公告)日：2012-07-19
申请号：US13498700
申请日：2011-04-14
申请人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
发明人： Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
IPC分类号： H01L29/786 , H01L21/336 , H01L21/50 , H01L27/06
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/124 , H01L27/1262 , H01L27/1292 , H01L27/3244 , H01L29/78603 , H01L2251/5338
摘要： Disclosed are a flexible semiconductor device and manufacturing method therefor whereby the capacitances of capacitor parts of semiconductor elements and the like can be increased while decreasing parasitic capacitances that arise between multilevel interconnections. The disclosed flexible semiconductor device is provided with an insulating film on which a semiconductor element is formed. The top and bottom surfaces of the insulating film have a top wiring pattern layer and a bottom wiring pattern layer, respectively. The semiconductor element comprises: a semiconductor layer formed on the top surface of the insulating film; a source electrode and a drain electrode formed on the top surface of the insulating film so as to contact the semiconductor layer; and a gate electrode formed on the bottom surface of the insulating film so as to be opposite the semiconductor layer. A first thickness, which is the thickness of the insulting film facing the source electrode, the drain electrode, the top wiring pattern layer, and the bottom wiring pattern layer, is greater than a second thickness, which is the thickness of the insulating film between the gate electrode and the semiconductor layer.
摘要翻译：公开了一种柔性半导体器件及其制造方法，由此可以增加半导体元件等的电容器部件的电容，同时减小在多层互连之间产生的寄生电容。所公开的柔性半导体器件设置有形成有半导体元件的绝缘膜。绝缘膜的顶表面和底表面分别具有顶部布线图案层和底部布线图案层。半导体元件包括：形成在绝缘膜的顶表面上的半导体层; 源电极和漏电极，形成在绝缘膜的顶表面上以与半导体层接触; 以及形成在绝缘膜的底表面上以与半导体层相对的栅电极。作为与源极电极，漏极电极，顶部布线图案层和底部布线图案层相对的绝缘膜的厚度的第一厚度大于第二厚度，其是绝缘膜的厚度栅电极和半导体层。

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