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1. 发明申请

US20120083121A1 Fabrication of Replacement Metal Gate Devices 有权
标题翻译：替代金属门装置的制造
公开(公告)号：US20120083121A1
公开(公告)日：2012-04-05
申请号：US13012879
申请日：2011-01-25
申请人： Takashi Ando , Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Takashi Ando , Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/463
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.
摘要翻译：用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。

2. 发明授权

US08507383B2 Fabrication of replacement metal gate devices 有权
标题翻译：替代金属栅极器件的制造
公开(公告)号：US08507383B2
公开(公告)日：2013-08-13
申请号：US13012879
申请日：2011-01-25
申请人： Takashi Ando , Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Takashi Ando , Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/302 , C03C15/00 , C23F1/00
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.
摘要翻译：用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。

3. 发明授权

US08524606B2 Chemical mechanical planarization with overburden mask 有权
标题翻译：化学机械平面化与上覆层掩模
公开(公告)号：US08524606B2
公开(公告)日：2013-09-03
申请号：US13012821
申请日：2011-01-25
申请人： Leslie Charns , John M. Cotte , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Leslie Charns , John M. Cotte , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/311
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.
摘要翻译：平面化方法包括在半导体晶片上的覆盖层顶部沉积掩模材料。将掩模材料平坦化以从覆盖层的上部区域去除掩模材料，以暴露覆盖层，而不从掩模材料向下区域移除。暴露的覆盖层被湿蚀刻并留下厚度保留在下层上。掩模层的剩余部分和覆盖层的暴露部分被平坦化以暴露下面的层。

4. 发明授权

US08513127B2 Chemical mechanical planarization processes for fabrication of FinFET devices 有权
标题翻译：用于制造FinFET器件的化学机械平面化工艺
公开(公告)号：US08513127B2
公开(公告)日：2013-08-20
申请号：US13012836
申请日：2011-01-25
申请人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
摘要翻译：平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在约1：1至约2：1：1，以提供平面形貌。

5. 发明授权

US08497210B2 Shallow trench isolation chemical mechanical planarization 有权
标题翻译：浅沟隔离化学机械平面化
公开(公告)号：US08497210B2
公开(公告)日：2013-07-30
申请号：US13012142
申请日：2011-01-24
申请人： Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.
摘要翻译：抛光方法包括在第一抛光剂中抛光晶片以去除覆盖层并平坦化顶层，留下保留在下层上的部分。第二抛光步骤包括两个阶段。在第一阶段中，去除顶层并暴露下层，其顶层至基层选择性为约1:1至约2:1，以提供平面形貌。在第二阶段中，顶层的残余部分从下层的顶部去除，以确保下层的表面完全曝光。

6. 发明申请

US20120083123A1 Chemical Mechanical Planarization Processes For Fabrication of FINFET Devices 有权
标题翻译：用于制造FINFET器件的化学机械平面化工艺
公开(公告)号：US20120083123A1
公开(公告)日：2012-04-05
申请号：US13012836
申请日：2011-01-25
申请人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Josephine B. Chang , Leslie Charns , Jason E. Cummings , Michael A. Guillorn , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/306
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
摘要翻译：平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在约1：1至约2：1：1，以提供平面形貌。

7. 发明申请

US20120083122A1 Shallow Trench Isolation Chemical Mechanical Planarization 有权
标题翻译：浅沟槽隔离化学机械平面化
公开(公告)号：US20120083122A1
公开(公告)日：2012-04-05
申请号：US13012142
申请日：2011-01-24
申请人： Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Leslie Charns , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lofaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/306
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.
摘要翻译：抛光方法包括在第一抛光剂中抛光晶片以去除覆盖层并平坦化顶层，留下保留在下层上的部分。第二抛光步骤包括两个阶段。在第一阶段中，去除顶层并暴露下层，其顶层至基层选择性为约1:1至约2:1，以提供平面形貌。在第二阶段中，顶层的残余部分从下层的顶部去除，以确保下层的表面完全曝光。

8. 发明申请

US20120083125A1 Chemical Mechanical Planarization With Overburden Mask 有权
标题翻译：化学机械平面化与覆盖面膜
公开(公告)号：US20120083125A1
公开(公告)日：2012-04-05
申请号：US13012821
申请日：2011-01-25
申请人： Leslie Charns , John M. Cotte , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lafaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
发明人： Leslie Charns , John M. Cotte , Jason E. Cummings , Lukasz J. Hupka , Dinesh R. Koli , Tomohisa Konno , Mahadevaiyer Krishnan , Michael F. Lafaro , Jakub W. Nalaskowski , Masahiro Noda , Dinesh K. Penigalapati , Tatsuya Yamanaka
IPC分类号： H01L21/311
CPC分类号： H01L21/31053 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.
摘要翻译：平面化方法包括在半导体晶片上的覆盖层顶部沉积掩模材料。将掩模材料平坦化以从覆盖层的上部区域去除掩模材料，以暴露覆盖层，而不从掩模材料向下区域移除。暴露的覆盖层被湿蚀刻并留下厚度保留在下层上。掩模层的剩余部分和覆盖层的暴露部分被平坦化以暴露下面的层。

9. 发明授权

US07955160B2 Glass mold polishing method and structure 有权
标题翻译：玻璃模具抛光方法和结构
公开(公告)号：US07955160B2
公开(公告)日：2011-06-07
申请号：US12135315
申请日：2008-06-09
申请人： Michael A. Cobb , Dinesh R. Koli , Michael F. Lofaro , Dennis G. Manzer , Paraneetha Poloju , James A. Tornello
发明人： Michael A. Cobb , Dinesh R. Koli , Michael F. Lofaro , Dennis G. Manzer , Paraneetha Poloju , James A. Tornello
IPC分类号： B24B1/00
CPC分类号： B24B37/042 , B24B37/11
摘要： A glass mold polishing structure and method. The method includes providing a polishing tool comprising mounting plate, a chuck plate over and mechanically attached to the mounting plate, and a pad structure over and mechanically attached to the chuck plate. A retaining structure is attached the chuck plate. A glass mold comprising a plurality of cavities is placed on the pad structure and within a perimeter formed by the retaining structure. A vacuum device is attached to the chuck plate. The vacuum device is activated such that a vacuum is formed and mechanically attaches the glass mold to the pad structure. The polishing tool comprising the glass mold mechanically attached to the pad structure is placed over and in contact with the polishing pad. The polishing tool comprising the glass mold is rotated. The glass mold is polished as a result of the rotation.
摘要翻译：玻璃模具抛光结构及方法。该方法包括提供一种抛光工具，该抛光工具包括安装板，卡盘板，并且机械地连接到安装板上，以及衬垫结构，并且在机械上附接到卡盘板上。保持结构安装在卡盘板上。包括多个空腔的玻璃模具被放置在垫结构上并且在由保持结构形成的周边内。真空装置安装在卡板上。激活真空装置，使得形成真空并将玻璃模具机械地附接到衬垫结构。包括机械地附接到垫结构的玻璃模具的抛光工具放置在抛光垫上并与抛光垫接触。包括玻璃模具的抛光工具旋转。玻璃模具由于旋转而被抛光。

10. 发明授权

US08889537B2 Implantless dopant segregation for silicide contacts 有权
标题翻译：用于硅化物接触的无植入物掺杂剂分离
公开(公告)号：US08889537B2
公开(公告)日：2014-11-18
申请号：US12833272
申请日：2010-07-09
申请人： Cryil Cabral, Jr. , John M. Cotte , Dinesh R. Koli , Laura L. Kosbar , Mahadevaiyer Krishnan , Christian Lavoie , Stephen M. Rossnagel , Zhen Zhang
发明人： Cryil Cabral, Jr. , John M. Cotte , Dinesh R. Koli , Laura L. Kosbar , Mahadevaiyer Krishnan , Christian Lavoie , Stephen M. Rossnagel , Zhen Zhang
IPC分类号： H01L21/28 , H01L21/285 , H01L29/45
CPC分类号： H01L21/28512 , H01L21/28518 , H01L29/456
摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.
摘要翻译：在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

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