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1. 发明申请

US20100079925A1 MULTILAYER CAPACITOR 有权
标题翻译：多层电容器
公开(公告)号：US20100079925A1
公开(公告)日：2010-04-01
申请号：US12497970
申请日：2009-07-06
申请人： Masaaki TOGASHI , Takashi AOKI
发明人： Masaaki TOGASHI , Takashi AOKI
IPC分类号： H01G4/232 , H01G4/30 , H01G4/005
CPC分类号： H01G4/005 , H01G4/232 , H01G4/30
摘要： A multilayer capacitor which can inhibit impedance from decreasing near a resonance frequency is provided.The multilayer capacitor comprises a dielectric matrix, a plurality of first and second inner electrodes, a pair of terminal electrodes, and a pair of linking electrodes. The first inner electrode has a first region located closer to a first terminal connection part than is a portion provided with a first linking connection part and a second region located closer to an opposite side of the first terminal connection part than is the portion provided with the first linking connection part. The second inner electrode has a third region located closer to a second terminal connection part than is a portion provided with a second linking connection part and a fourth region located closer to an opposite side of the second terminal connection part than is the portion provided with the second linking connection part. The first region has an area smaller than that of the fourth region, while the third region has an area smaller than that of the second region.
摘要翻译：提供了可以抑制阻抗在谐振频率附近降低的层叠电容器。多层电容器包括介质矩阵，多个第一和第二内部电极，一对端子电极和一对连接电极。第一内部电极具有比设置有第一连接连接部的部分更靠近第一端子连接部的第一区域和位于比第一端子连接部的相对侧更靠近第二区域的部分，第一连接部分。第二内部电极具有比设置有第二连接部的部分更靠近第二端子连接部的第三区域和位于比第二端子连接部更靠近第二端子连接部的相反侧的部分，第二连接部。第一区域的面积小于第四区域的面积，而第三区域的面积小于第二区域的面积。

2. 发明申请

US20120250218A1 FEEDTHROUGH MULTILAYER CAPACITOR 有权
标题翻译：生产多层电容器
公开(公告)号：US20120250218A1
公开(公告)日：2012-10-04
申请号：US13415431
申请日：2012-03-08
申请人： Masaaki TOGASHI , Takashi AOKI , Hiroshi OKUYAMA , Yutaro KOTANI
发明人： Masaaki TOGASHI , Takashi AOKI , Hiroshi OKUYAMA , Yutaro KOTANI
IPC分类号： H01G4/35
CPC分类号： H01G4/30 , H01G4/232 , H01G4/35
摘要： A conducting portion includes a plurality of conducting inner electrodes. Each of a pair of capacitance portions includes a plurality of signal inner electrodes while adjacently opposing each other in the laminating direction, a plurality of first grounding inner electrodes while adjacently opposing each other in the laminating direction, and a plurality of second grounding inner electrodes while adjacently opposing each other in the laminating direction. The plurality of first grounding inner electrodes are located between the conducting portion and the plurality of signal inner electrodes, while one of the first grounding inner electrodes adjacently opposes one of the first signal inner electrodes in the laminating direction. The plurality of second grounding inner electrodes are located between principal faces opposing each other in the laminating direction in the outer surface and the plurality of signal inner electrodes.
摘要翻译：导电部分包括多个导电内部电极。一对电容部分中的每一个包括多个信号内部电极，同时在层叠方向上相互相对，多个第一接地内部电极在层叠方向上彼此相邻;多个第二接地内部电极，同时在层叠方向上彼此相邻地相对。所述多个第一接地内部电极位于所述导通部和所述多个信号内部电极之间，所述第一接地内部电极中的一个在所述层叠方向上与所述第一信号内部电极之一相邻地相对。多个第二接地内电极位于外表面和多个信号内电极的层叠方向上彼此相对的主面之间。

3. 发明申请

US20090147439A1 MULTILAYER CAPACITOR ARRAY 有权
标题翻译：多层电容阵列
公开(公告)号：US20090147439A1
公开(公告)日：2009-06-11
申请号：US12274790
申请日：2008-11-20
申请人： Masaaki TOGASHI , Takashi AOKI
发明人： Masaaki TOGASHI , Takashi AOKI
IPC分类号： H01G4/232
CPC分类号： H01G4/232 , H01G4/005 , H01G4/30
摘要： At least one of a plurality of first internal electrodes and a second internal electrode are arranged as opposed with at least one of the dielectric layers in between. Third and fourth internal electrodes are arranged as opposed with at least one of the dielectric layers in between. The first internal electrodes are electrically connected to a first external connecting conductor through lead conductors. The second, third, and fourth internal electrodes are electrically connected to second, third, and fourth terminal conductors, respectively, through lead conductors. At last one but not all of the first internal electrodes are electrically connected to the first terminal conductor through a lead conductor.
摘要翻译：多个第一内部电极和第二内部电极中的至少一个布置成与其间的至少一个电介质层相对。第三和第四内部电极被布置成与其间的至少一个电介质层相对。第一内部电极通过引线导体电连接到第一外部连接导体。第二，第三和第四内部电极分别通过引线导体电连接到第二，第三和第四端子导体。最后一个但不是全部的第一内部电极通过引线导体与第一端子导体电连接。

4. 发明申请

US20100095498A1 METHODS OF PRODUCING MULTILAYER CAPACITOR 失效
标题翻译：生产多层电容器的方法
公开(公告)号：US20100095498A1
公开(公告)日：2010-04-22
申请号：US12537834
申请日：2009-08-07
申请人： Takashi AOKI , Masaaki TOGASHI
发明人： Takashi AOKI , Masaaki TOGASHI
IPC分类号： H01G4/12
CPC分类号： H01G4/012 , H01G4/232 , H01G4/30 , Y10T29/417 , Y10T29/435 , Y10T29/49004
摘要： A method of producing a multilayer capacitor has a step of preparing a plurality of first ceramic green sheets, a step of preparing a plurality of second ceramic green sheets, a step of laminating the plurality of first and second ceramic green sheets, and a step of cutting a ceramic green sheet laminate body along predetermined intended cutting lines to obtain laminate chips of individual multilayer capacitor units. In the step of preparing the first ceramic green sheets, first and second internal electrode patterns are formed so that the first and second internal electrode patterns are alternately arranged in a predetermined direction and in a direction perpendicular to the predetermined direction and so that portions corresponding to lead portions of first and second internal electrodes in the first and second internal electrode patterns are continuous across the predetermined intended cutting line. In the step of preparing the second ceramic green sheets, third and fourth internal electrode patterns are formed so that the third and fourth internal electrode patterns are alternately arranged in the predetermined direction and in the direction perpendicular to the predetermined direction and so that portions corresponding to lead portions of third and fourth internal electrodes in the third and fourth internal electrode patterns are continuous across the predetermined intended cutting lines.
摘要翻译：制备多层电容器的方法具有制备多个第一陶瓷生片的步骤，制备多个第二陶瓷生片的步骤，层叠多个第一和第二陶瓷生片的步骤，以及步骤沿着预定的切割线切割陶瓷生片层压体，以获得各层叠电容器单元的层压片。在制备第一陶瓷生片的步骤中，形成第一和第二内部电极图案，使得第一和第二内部电极图案沿预定方向和垂直于预定方向的方向交替布置，并且使得与第一和第二内部电极图案中的第一和第二内部电极的引线部分跨越预定的预定切割线是连续的。在制备第二陶瓷生片的步骤中，形成第三和第四内部电极图案，使得第三和第四内部电极图案沿预定方向和垂直于预定方向的方向交替布置，并且使得与第三和第四内部电极图案中的第三和第四内部电极的引线部分跨越预定的预定切割线是连续的。

5. 发明申请

US20120120546A1 FEED-THROUGH CAPACITOR AND FEED-THROUGH CAPACITOR MOUNTING STRUCTURE 有权
标题翻译：馈电电容器和馈电电容器安装结构
公开(公告)号：US20120120546A1
公开(公告)日：2012-05-17
申请号：US13234807
申请日：2011-09-16
申请人： Masaaki TOGASHI , Takashi AOKI
发明人： Masaaki TOGASHI , Takashi AOKI
IPC分类号： H01G4/35 , H05K7/02
CPC分类号： H01G4/35 , H01G4/012 , H01G4/30
摘要： In a feed-through capacitor, a conduction unit having a plurality of conduction inner electrodes can fully secure a tolerable level of DC. A capacitor unit is formed on the mount surface side in a capacitor body, so that high-frequency noise components can be removed by the capacitor unit before reaching the conduction unit. The distance between the grounding inner electrode located closest to the conduction unit and the conduction inner electrode in the conduction unit is greater than that between the signal inner electrode and grounding inner electrode in the capacitor unit. This enhances the impedance between the capacitor unit and the conduction unit, so as to inhibit the high-frequency noise components from flowing into the conduction unit.
摘要翻译：在馈通电容器中，具有多个导电内部电极的导电单元可以完全确保可容许的DC电平。在电容器体的安装面侧形成有电容器单元，从而在到达导通单元之前可以通过电容器单元除去高频噪声成分。位于最靠近导电单元的接地内部电极与导电单元中的导电内部电极之间的距离大于电容器单元中的信号内部电极与接地内部电极之间的距离。这增强了电容器单元和导电单元之间的阻抗，以便抑制高频噪声分量流入导通单元。

6. 发明申请

US20090161288A1 MULTILAYER CAPACITOR ARRAY 有权
标题翻译：多层电容阵列
公开(公告)号：US20090161288A1
公开(公告)日：2009-06-25
申请号：US12274868
申请日：2008-11-20
申请人： Masaaki TOGASHI , Takashi AOKI
发明人： Masaaki TOGASHI , Takashi AOKI
IPC分类号： H01G4/005 , H01G4/228
CPC分类号： H01G4/005 , H01G4/232
摘要： Among a plurality of first inner electrodes, at least one first inner and a second inner electrode are arranged as opposed with at least one of the dielectric layers in between. Third and fourth inner electrodes are arranged as opposed with at least one of the dielectric layers in between. The first inner electrodes are electrically connected to a first external connection conductor via lead conductors. The second inner electrode is electrically connected to a second terminal conductor via a lead conductor. The third inner electrode is electrically connected to a third terminal conductor via a lead conductor. The fourth inner electrode is electrically connected to a fourth terminal conductor via a lead conductor. Among all the first inner electrodes, one to multiple first inner electrodes that are less than the total first inner electrodes are electrically connected to the first terminal conductors via lead conductors.
摘要翻译：在多个第一内部电极中，至少一个第一内部电极和第二内部电极被布置成与其间的至少一个电介质层相对。第三和第四内部电极被布置成与其间的介电层中的至少一个相对。第一内部电极通过引线导体电连接到第一外部连接导体。第二内部电极经由引线导体电连接到第二端子导体。第三内部电极经由引线导体与第三端子导体电连接。第四内部电极经由引线导体与第四端子导体电连接。在所有第一内部电极中，小于总第一内部电极的一个至多个第一内部电极经由引线导体电连接到第一端子导体。

7. 发明申请

US20090231779A1 MULTILAYER CAPACITOR AND MOUNTED STRUCTURE THEREOF 有权
标题翻译：多层电容器及其安装结构
公开(公告)号：US20090231779A1
公开(公告)日：2009-09-17
申请号：US12362041
申请日：2009-01-29
申请人： Takashi AOKI
发明人： Takashi AOKI
IPC分类号： H01G4/30 , H01G4/228
CPC分类号： H01G4/33 , H01G4/005 , H01G4/232
摘要： In a multilayer capacitor, widths of lead conductors of internal electrode and widths of lead conductors of internal electrode in an ESR control section are smaller than any one of widths of internal electrode and widths of internal electrode in a capacitance section. This narrows cross sections of the conductor portions connecting between the internal electrodes and the external electrodes, so as to her increase ESR. The widths of the respective lead conductors in the ESR control section are wider than widths of respective lead conductors in the capacitance section. This effectively prevents open failure and improves a yield of products.
摘要翻译：在层叠电容器中，ESR控制部内部电极的引线导体的宽度和内部电极的引出导体的宽度比电容部的内部电极的宽度和内部电极的宽度小。这使得内部电极和外部电极之间连接的导体部分的横截面变窄，从而使ESR增加。 ESR控制部分中的各个引线导体的宽度比电容部分中引线导体的宽度宽。这有效地防止了开路故障并提高了产品的产量。

8. 发明申请

US20080239616A1 MULTILAYER CAPACITOR ARRAY 有权
标题翻译：多层电容阵列
公开(公告)号：US20080239616A1
公开(公告)日：2008-10-02
申请号：US12051316
申请日：2008-03-19
申请人： Takashi AOKI
发明人： Takashi AOKI
IPC分类号： H01G4/30
CPC分类号： H01G4/012 , H01G4/232 , H01G4/30
摘要： A multilayer capacitor array comprises a capacitor body having rectangular first and second main faces opposing each other. In the capacitor body having a dielectric characteristic, first inner electrodes are arranged in a first region, second inner electrodes are arranged in a second region, and third and fourth inner electrodes are arranged so as to extend over the first and second regions. Each of the third inner electrodes opposes at least one of the first inner electrodes and at least one of the second inner electrodes. Each of the fourth inner electrodes opposes at least one of the first inner electrodes and at least one of the second inner electrodes. The third inner electrodes are adjacent to the fourth inner electrodes, respectively.
摘要翻译：一种层叠电容器阵列包括具有彼此相对的矩形第一和第二主表面的电容器本体。在具有介电特性的电容器主体中，第一内部电极配置在第一区域中，第二内部电极配置在第二区域中，第三和第四内部电极被布置成在第一和第二区域上延伸。第三内电极中的每一个与第一内电极和第二内电极中的至少一个相对。第四内电极中的每一个与第一内电极和第二内电极中的至少一个相对。第三内电极分别与第四内电极相邻。

9. 发明申请

US20080217609A1 ORGANIC TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING THE SAME 有权
标题翻译：有机晶体管，其制造方法和包括其的电子设备
公开(公告)号：US20080217609A1
公开(公告)日：2008-09-11
申请号：US12034684
申请日：2008-02-21
申请人： Takashi AOKI
发明人： Takashi AOKI
IPC分类号： H01L51/00 , H01L21/00
CPC分类号： H01L51/0541 , H01L51/0005 , H01L51/0036 , H01L51/0037
摘要： An organic transistor includes a source electrode and a drain electrode, an organic semiconductor layer disposed across between the source electrode and the drain electrode, a gate insulating layer, and a gate electrode opposing the source and drain electrodes with the organic semiconductor layer and the gate insulating layer therebetween. The organic semiconductor layer includes a first semiconductor portion in a region where the gate electrode and the source electrode oppose each other, a second semiconductor portion in a region where the gate electrode and the drain electrode oppose each other, and a third semiconductor portion between the first semiconductor portion and the second semiconductor portion. The first semiconductor portion, the second semiconductor portion, and the third semiconductor portion satisfy the relationships W1
摘要翻译：有机晶体管包括源电极和漏电极，设置在源电极和漏电极之间的有机半导体层，栅极绝缘层和与源极和漏极电极相对的有机半导体层和栅极的栅电极绝缘层。有机半导体层包括在栅电极和源极彼此相对的区域中的第一半导体部分，栅电极和漏电极彼此相对的区域中的第二半导体部分，以及位于第一半导体部分和第二半导体部分。第一半导体部分，第二半导体部分和第三半导体部分满足关系W 1

10. 发明申请

US20120306819A1 INPUT FUNCTION DISPLAY DEVICE 审中-公开
标题翻译：输入功能显示设备
公开(公告)号：US20120306819A1
公开(公告)日：2012-12-06
申请号：US13482315
申请日：2012-05-29
申请人： Katsunori YAMAZAKI , Takashi AOKI
发明人： Katsunori YAMAZAKI , Takashi AOKI
IPC分类号： G09G3/34 , G06F3/042
CPC分类号： G02F1/167 , G02F1/13338 , G06F3/0321 , G06F3/033 , G06F3/03542 , G06F3/03545 , G06F3/041 , G09F9/37 , G09G3/344
摘要： An input function display device includes: a display unit to which a position information pattern representing a coordinate position is given; and a position information reading unit that reads the position information pattern using invisible light, in which the display unit includes an electrophoretic element, a first substrate having a first electrode on a face of the electrophoretic element side, and a second substrate having a second electrode on a face of the electrophoretic element side, and any one of a constituent member of the electrophoretic element and the position information pattern has reflectance with respect to invisible light, and the other has absorptiveness. The display unit performs displaying on the basis of marks read from the position information pattern by the position information reading unit.
摘要翻译：输入功能显示装置包括：给出表示坐标位置的位置信息图案的显示单元; 以及位置信息读取单元，其使用不可见光读取位置信息图案，其中显示单元包括电泳元件，在电泳元件侧的表面上具有第一电极的第一基板和具有第二电极的第二基板在电泳元件侧的面上，电泳元件的构成构件和位置信息图案中的任一个相对于不可见光具有反射率，另一个具有吸收性。显示单元基于由位置信息读取单元从位置信息模式读取的标记来执行显示。

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