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1. 发明授权

US08299816B2 Data processing apparatus 有权
标题翻译：数据处理装置
公开(公告)号：US08299816B2
公开(公告)日：2012-10-30
申请号：US12891352
申请日：2010-09-27
申请人： Kazuo Yamada , Takao Naito
发明人： Kazuo Yamada , Takao Naito
IPC分类号： H03K19/173 , G06F15/00
CPC分类号： G06F15/7878 , H03K19/17752
摘要： A data processing apparatus includes a reconfigurable circuit capable of reconfigurating partially a circuit configuration: and a reconfiguration controlling unit that controls a reconfiguration of the circuit configuration of the reconfigurable circuit. The reconfiguration controlling unit reconfigurates a plurality of partial circuits, which constitute one pipeline and are reconfigurated simultaneously on the reconfigurable circuit, on the reconfigurable circuit in sequence from a head partial circuit of the pipeline, and starts sequentially the reconfigurated partial circuits from a head.
摘要翻译：数据处理装置包括能够部分地重新配置电路配置的可重新配置电路;以及重新配置控制单元，其控制可重新配置电路的电路配置的重新配置。重新配置控制单元重新配置构成一个流水线的多个部分电路，并且在可重构电路上同时重新配置在可重新配置的电路上，从流水线的头部分电路依次重新配置，并从头开始依次重新配置部分电路。

2. 发明授权

US08719550B2 Reconfigurable processing system including synchronized postprocessing 有权
标题翻译：可重构处理系统包括同步后处理
公开(公告)号：US08719550B2
公开(公告)日：2014-05-06
申请号：US12869200
申请日：2010-08-26
申请人： Takao Naito , Kazuo Yamada
发明人： Takao Naito , Kazuo Yamada
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/7867 , G06F17/5054
摘要： Source code to be processed is analyzed and configuration data in implementing in accordance with each of plural implementation systems is created and is stored in a local memory of a DRP incorporating system. When execution of target processing is started, the implementation system determination processing calculates estimated processing time when the configuration of each of the implementation systems is adopted and determines the optimum one of the implementation systems based on a combination of the estimated processing time and the circuit scale of the configuration.
摘要翻译：分析要处理的源代码，并且根据多个实现系统中的每一个实现的配置数据被创建并存储在DRP并入系统的本地存储器中。当执行目标处理开始时，执行系统确定处理计算当采用每个实现系统的配置时的估计处理时间，并且基于估计的处理时间和电路规模的组合来确定实现系统中的最佳一个的配置。

3. 发明授权

US08656140B2 Data processing device 有权
标题翻译：数据处理装置
公开(公告)号：US08656140B2
公开(公告)日：2014-02-18
申请号：US12963072
申请日：2010-12-08
申请人： Kazuo Yamada , Takao Naito
发明人： Kazuo Yamada , Takao Naito
IPC分类号： G06F13/00
CPC分类号： G06F13/1663
摘要： An internal buffer is provided for a DRP core. A selector SEL switches input/output destination of the DRP core between external memory and an internal buffer. Control software executed by a CPU core receives information a pipeline of configurations for a sequence of target processing and generates combinations as to whether the processing result is transferred between the configurations via the external memory or via the internal buffer as transfer manners. Next, for each manner, bandwidth and performance of the external memory used by the DRP core in the manner are calculated. The manner of the best performance satisfying a previously specified bandwidth restriction is selected among the manners and the selector SEL is switched in accordance with the manner.
摘要翻译：为DRP内核提供内部缓冲区。选择器SEL在外部存储器和内部缓冲器之间切换DRP内核的输入/输出目的地。由CPU核心执行的控制软件接收关于目标处理序列的配置流水线的信息，并且通过外部存储器或经由内部缓冲器作为传送方式生成关于处理结果是否在配置之间传送的组合。接下来，对于每种方式，计算由DRP核心使用的外部存储器的带宽和性能。以这种方式选择满足先前指定的带宽限制的最佳性能的方式，并且根据该方式切换选择器SEL。

4. 发明授权

US08587793B2 Print image processing apparatus and computer readable medium 有权
标题翻译：打印图像处理装置和计算机可读介质
公开(公告)号：US08587793B2
公开(公告)日：2013-11-19
申请号：US12912278
申请日：2010-10-26
申请人： Takao Naito , Kazuo Yamada
发明人： Takao Naito , Kazuo Yamada
IPC分类号： G06F3/12 , G06K9/54
CPC分类号： G06F3/1215 , G06F3/124 , G06F3/1247 , G06F3/1279 , G06F3/1282 , G06K15/1823 , G06K15/1849 , G06K15/1851 , G06K15/1857
摘要： A print image processing apparatus, includes N image processing circuits; a selection unit that estimates, every N pages, a necessary time corresponding to each of (i) a page-based parallel method for allocating image processing of the N pages to the image processing circuits in units of pages to perform the image processing of the N pages in parallel, and (ii) a paginal-object-based parallel method for allocating image processing of each single page to the image processing circuits in units of objects to perform the image processing of the objects of each single page in parallel, and selects one of the page-based parallel method and the paginal-object-based parallel method such that the estimated necessary time corresponding to the selected one of the parallel methods is shorter than the estimated necessary time; and an allocation unit that allocates image processing of the N pages to the N image processing circuit, respectively.
摘要翻译：一种打印图像处理装置，包括N个图像处理电路; 每个N页面估计每个N页面所需的时间的必要时间，所述必要时间对应于（i）用于以页为单位将N页的图像处理分配给图像处理电路的基于页的并行方法，以执行图像处理 N页并行，以及（ii）基于对象的并行方法，用于以对象为单位将每个单页的图像处理分配给图像处理电路，以并行地执行每个单页的对象的图像处理;以及选择基于页面的并行方法和基于对象的并行方法之一，使得与所选择的并行方法中的一个并行方法相对应的估计必要时间短于估计的必要时间; 以及分配单元，其将N个页面的图像处理分别分配给N个图像处理电路。

5. 发明授权

US08554003B2 Image data processing apparatus, image data processing method, and computer readable medium 有权
标题翻译：图像数据处理装置，图像数据处理方法和计算机可读介质
公开(公告)号：US08554003B2
公开(公告)日：2013-10-08
申请号：US13295405
申请日：2011-11-14
申请人： Takao Naito , Kazuo Yamada
发明人： Takao Naito , Kazuo Yamada
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： G06T1/20
摘要： An image data processing apparatus includes the following elements. A lossless compression device performs lossless compression. A configuration controller performs control so that a first configuration including a first line memory set and a decompression circuit set and a second configuration including a second line memory set are selectively set in a reconfigurable circuit. A maximum size determining device determines the maximum size of lines of the compressed image data. An output controller performs control so that, when the maximum size is equal to or smaller than a predetermined threshold, the first configuration is set and the compressed image data is output to an image processing circuit via the first line memory set, and so that, when the maximum size is greater than the predetermined threshold, the second configuration is set and the non-compressed image data is output to the image processing circuit via the second line memory set.
摘要翻译：图像数据处理装置包括以下要素。无损压缩装置执行无损压缩。配置控制器执行控制，使得在可重新配置的电路中选择性地设置包括第一行存储器组和解压缩电路组的第一配置以及包括第二行存储器组的第二配置。最大尺寸确定装置确定压缩图像数据的行的最大尺寸。输出控制器执行控制，使得当最大尺寸等于或小于预定阈值时，设置第一配置，并且经由第一行存储器将经压缩的图像数据输出到图像处理电路，当最大尺寸大于预定阈值时，设置第二配置，并且经由第二行存储器组将非压缩图像数据输出到图像处理电路。

6. 发明授权

US08831012B2 Determining paths in a network with asymmetric switches 有权
标题翻译：确定具有非对称开关的网络中的路径
公开(公告)号：US08831012B2
公开(公告)日：2014-09-09
申请号：US12574972
申请日：2009-10-07
申请人： Min He , Kevin Zhu , Srinivas Vobilisetti , Takao Naito , Paparao Palacharla , Xi Wang , Qiong Zhang
发明人： Min He , Kevin Zhu , Srinivas Vobilisetti , Takao Naito , Paparao Palacharla , Xi Wang , Qiong Zhang
IPC分类号： H04L12/28 , H04L12/46 , H04L12/701 , H04L12/721 , H04L12/735 , H04L12/707 , H04Q3/66
CPC分类号： H04L12/462 , H04L45/00 , H04L45/12 , H04L45/128 , H04L45/22 , H04Q3/66 , H04Q2213/13141 , H04Q2213/13148
摘要： According to particular embodiments, determining paths in a network with asymmetric switches includes receiving a graph representing the network. Each asymmetric switch has defined degree connectivity between one or more pairs of degrees of the asymmetric switch. The graph is transformed to yield a transformed graph that accounts for the asymmetric switches. A routing process is applied to the transformed graph to yield one or more paths through the network.
摘要翻译：根据特定实施例，使用非对称交换机确定网络中的路径包括接收表示网络的图形。每个非对称开关已经限定了非对称开关的一对或多对度之间的程度连接。转换图形以产生解释非对称开关的变换图。将路由过程应用于变换图，以产生通过网络的一个或多个路径。

7. 发明授权

US08750127B2 Systems and methods for multi-domain routing 有权
标题翻译：多域路由的系统和方法
公开(公告)号：US08750127B2
公开(公告)日：2014-06-10
申请号：US12751656
申请日：2010-03-31
申请人： Qiong Zhang , Mohammad Masud Hasan , Xi Wang , Paparao Palacharla , Takao Naito , Fredrick S. Gruman
发明人： Qiong Zhang , Mohammad Masud Hasan , Xi Wang , Paparao Palacharla , Takao Naito , Fredrick S. Gruman
IPC分类号： H04L1/00 , H04L12/26 , H04L12/56
CPC分类号： H04L45/12 , H04L45/00 , H04L45/02 , H04L45/04 , H04L45/126 , H04L45/128 , H04L45/22 , H04L45/28
摘要： Systems and methods for multi-domain routing are provided. In some embodiments, a method for determining a path calculation from a source node to a destination node over a multi-domain network is provided. The method may include steps for receiving a predetermined sequence of domains for communicating information from the source node to the destination node, determining a link type for each of a plurality of links in the predetermined sequence of domains, modifying the link type of one or more of the plurality of links such that the plurality of links are unidirectional links towards a destination node, and determining a path along the predetermined sequence of domains based on the modified plurality of links.
摘要翻译：提供了多域路由的系统和方法。在一些实施例中，提供了一种用于确定通过多域网络从源节点到目的地节点的路径计算的方法。该方法可以包括用于接收用于将信息从源节点传送到目的地节点的预定的域序列的步骤，为预定的域序列中的多个链路中的每一个确定链路类型，修改一个或多个链路类型所述多个链路使得所述多个链路是朝向目的地节点的单向链路，以及基于所述修改的多个链路来确定沿着所述预定的域序列的路径。

8. 发明授权

US08681634B2 Systems and methods for determining protection paths in a multi-domain network 有权
标题翻译：用于确定多域网络中的保护路径的系统和方法
公开(公告)号：US08681634B2
公开(公告)日：2014-03-25
申请号：US12751599
申请日：2010-03-31
申请人： Qiong Zhang , Mohammad Masud Hasan , Xi Wang , Paparao Palacharla , Takao Naito , Fredrick S. Gruman
发明人： Qiong Zhang , Mohammad Masud Hasan , Xi Wang , Paparao Palacharla , Takao Naito , Fredrick S. Gruman
IPC分类号： H04L12/26
CPC分类号： H04L45/04 , H04L45/128 , H04L45/22 , H04L45/24 , H04L45/28
摘要： Systems and methods for determining multiple paths in a multi-domain network are provided. In some embodiments, a method for determining multiple paths in a network is provided. The method may include determining a first path between a source node and a destination node and determining a second path disjoint from the first path. In some embodiments, to determine the second path includes determining which ingress nodes are available in a domain that includes the destination node, where the available ingress nodes are not part of the first path, and implementing a disjoint path algorithm for each of the available ingress nodes. To determine the first path includes implementing forward path calculations.
摘要翻译：提供了用于确定多域网络中的多个路径的系统和方法。在一些实施例中，提供了一种用于确定网络中的多个路径的方法。该方法可以包括确定源节点和目的地节点之间的第一路径并确定与第一路径不相交的第二路径。在一些实施例中，为了确定第二路径包括确定哪些入口节点在包括目的地节点的域中是可用的，其中可用入口节点不是第一路径的一部分，并且为每个可用入口实现不相交路径算法节点。确定第一条路径包括实现前向路径计算。

9. 发明授权

US08347006B2 Minimizing interconnections in a multi-shelf switching system 有权
标题翻译：最大限度地减少多层交换系统中的互连
公开(公告)号：US08347006B2
公开(公告)日：2013-01-01
申请号：US12683504
申请日：2010-01-07
申请人： Qiong Zhang , Paparao Palacharla , Xi Wang , Takao Naito
发明人： Qiong Zhang , Paparao Palacharla , Xi Wang , Takao Naito
IPC分类号： G06F13/00 , G06F17/50 , G06G7/62
CPC分类号： H04L47/10 , H04L41/12
摘要： In certain embodiments, minimizing interconnections in a multi-shelf switching system includes receiving a map describing the switching system, where the switching system comprises shelves and input/output (I/O) points. The map is transformed to yield a graph comprising nodes and edges. A node represents an I/O point, and a node weight represents a number of interface cards of the I/O point represented by the node. An edge between a node pair represents traffic demand between the I/O points represented by the node pair, and an edge weight represents the amount of the traffic demand represented by the edge. The graph is partitioned to yield a groups that minimize interconnection traffic among the shelves, where each group represents a shelf of the multi-shelf switching system.
摘要翻译：在某些实施例中，最小化多货架交换系统中的互连包括接收描述交换系统的映射，其中交换系统包括货架和输入/输出（I / O）点。该图被变换以产生包括节点和边的图。节点表示I / O点，节点权重表示由节点表示的I / O点的接口卡数量。节点对之间的边缘表示由节点对表示的I / O点之间的业务需求，边缘权重表示由边缘表示的业务量需求量。该图被分割以产生使架之间的互连流量最小化的组，其中每个组表示多货架交换系统的货架。

10. 发明授权

US08218975B2 Free-space DQPSK demodulator 有权
标题翻译：自由空间DQPSK解调器
公开(公告)号：US08218975B2
公开(公告)日：2012-07-10
申请号：US12650663
申请日：2009-12-31
申请人： Cechan Tian , Takao Naito
发明人： Cechan Tian , Takao Naito
IPC分类号： H04B10/06
CPC分类号： H04B10/677
摘要： A demodulator comprises an input splitter, optical device sets, and couplers. The input splitter splits an input signal comprising symbols to yield a number of signals. A first optical device set directs a signal of along a first path. A second optical device set directs another signal along a second path to yield a delayed signal. At least a portion of the second path is in free space. A path length difference between the first path and the second path introduces a delay between the first signal and the second signal. A coupler receives a portion of the signal and a portion of the delayed signal to generate interference, where the interference indicates a phase shift between a phase corresponding to a symbol and a successive phase corresponding to a successive symbol.
摘要翻译：解调器包括输入分配器，光学器件组和耦合器。输入分路器分离包括符号的输入信号以产生多个信号。第一光学装置组引导沿着第一路径的信号。第二光学装置组沿着第二路径引导另一个信号以产生延迟的信号。第二路径的至少一部分在自由空间中。第一路径和第二路径之间的路径长度差引入第一信号和第二信号之间的延迟。耦合器接收信号的一部分和延迟信号的一部分以产生干扰，其中干扰表示对应于符号的相位和对应于连续符号的连续相位之间的相移。

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