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1. 发明授权

US07228377B2 Semiconductor integrated circuit device, IC card, and mobile terminal 有权
标题翻译：半导体集成电路器件，IC卡和移动终端
公开(公告)号：US07228377B2
公开(公告)日：2007-06-05
申请号：US10857888
申请日：2004-06-02
申请人： Takanori Yamazoe , Takashi Tase , Junji Shigeta , Nobutaka Nagasaki , Eiji Yamasaki , Nobuhiro Oodaira , Kozo Katayama
发明人： Takanori Yamazoe , Takashi Tase , Junji Shigeta , Nobutaka Nagasaki , Eiji Yamasaki , Nobuhiro Oodaira , Kozo Katayama
IPC分类号： G06F12/00
CPC分类号： G06K19/077 , G06F12/0893 , G06F2212/2022 , G11C16/04 , G11C16/0466 , G11C16/102 , G11C16/105 , H01L27/115 , H01L27/11568
摘要： In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.
摘要翻译：本发明提供了一种能够将EEPROM容量限制在最小必需量并减少芯片面积的技术，其中配备有闪存和EEPROM的半导体集成电路装置是非易失性存储器。一个应用程序所需的最小尺寸数据和频繁重写的数据存储在EEPROM中，并且EEPROM被配置为具有大约最小尺寸的容量。由其他应用程序分别处理并经常重写的相同大小的数据被存储在闪速存储器中。对于实际使用的应用，存储在闪速存储器中的数据被传送到EEPROM并使用。必要时，执行闪速存储器与EEPROM之间的数据传输。因此，可以减小EEPROM容量并且可以实现芯片面积的减小。

2. 发明授权

US08050085B2 Semiconductor processing device and IC card 有权
标题翻译：半导体处理装置和IC卡
公开(公告)号：US08050085B2
公开(公告)日：2011-11-01
申请号：US10521553
申请日：2002-08-29
申请人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
发明人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
IPC分类号： G11C7/10 , G11C11/40
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/40975 , G07F7/084 , G11C11/005 , G11C16/0425 , G11C16/0433 , G11C16/16
摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.
摘要翻译：根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及中央处理单元（2），能够从/向外部输入/输出加密数据。第一非易失性存储器用于存储要用于加密数据的加密密钥。第二非易失性存储器用于存储要由中央处理单元处理的程序。用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息处理CPU。

3. 发明申请

US20090213649A1 Semiconductor processing device and IC card 有权
标题翻译：半导体处理装置和IC卡
公开(公告)号：US20090213649A1
公开(公告)日：2009-08-27
申请号：US10521553
申请日：2002-08-29
申请人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
发明人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
IPC分类号： G11C11/34 , G11C16/04 , G11C5/14 , G06F12/14
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/40975 , G07F7/084 , G11C11/005 , G11C16/0425 , G11C16/0433 , G11C16/16
摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.
摘要翻译：根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及中央处理单元（2），能够从/向外部输入/输出加密数据。第一非易失性存储器用于存储要用于加密数据的加密密钥。第二非易失性存储器用于存储要由中央处理单元处理的程序。用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息处理CPU。

4. 发明授权

US07221610B2 Charge pump circuit for generating high voltages required in read/write/erase/standby modes in non-volatile memory device 有权
标题翻译：用于在非易失性存储器件中产生读/写/擦除/待机模式所需的高电压的电荷泵电路
公开(公告)号：US07221610B2
公开(公告)日：2007-05-22
申请号：US11050753
申请日：2005-02-07
申请人： Takanori Yamazoe , Yuichiro Akimoto , Hisanobu Ishida , Eiji Yamasaki , Nobuhiro Oodaira
发明人： Takanori Yamazoe , Yuichiro Akimoto , Hisanobu Ishida , Eiji Yamasaki , Nobuhiro Oodaira
IPC分类号： G11C5/14
CPC分类号： G11C16/12
摘要： Different stepped-up voltages and different output currents are generated in one charge pump circuit without increasing the chip area of the charge pump circuit and also electric power consumption in the charge pump circuit to be reduced to a very low power consumption level in standby mode and other modes. A semiconductor integrated circuit device comprises one charge pump circuit with an N number of basic pump cell stages connected to step up voltages in the erase and write modes of a non-volatile memory or the like, generates stepped-up voltages lower than in the erase and write modes and different from one another in output current supply capability, by using series- or parallel-connected pump cells not in excess of the N number of pump cell stages mentioned above, and changes a voltage step-up clock to a stepped-up voltage detection signal.
摘要翻译：在一个电荷泵电路中产生不同的升压电压和不同的输出电流，而不增加电荷泵电路的芯片面积，并且电荷泵电路中的电功率消耗在待机模式下降低到非常低的功率消耗水平，其他模式。半导体集成电路装置包括一个电荷泵电路，其中N个基本泵浦电池级连接到非易失性存储器等的擦除和写入模式中的升压电压，产生比在擦除中低的升压电压并通过使用不超过上述N个泵浦电池级的串并联连接的泵浦电池将输出电流供应能力的写入模式彼此不同，并将升压时钟更改为阶梯式上电压检测信号。

5. 发明申请

US20050207236A1 Charge pump circuit and non-volatile memory using the same 有权
标题翻译：电荷泵电路和非易失性存储器使用相同
公开(公告)号：US20050207236A1
公开(公告)日：2005-09-22
申请号：US11050753
申请日：2005-02-07
申请人： Takanori Yamazoe , Yuichiro Akimoto , Hisanobu Ishida , Eiji Yamasaki , Nobuhiro Oodaira
发明人： Takanori Yamazoe , Yuichiro Akimoto , Hisanobu Ishida , Eiji Yamasaki , Nobuhiro Oodaira
IPC分类号： G11C16/06 , G11C16/04 , G11C16/10 , G11C16/12 , H02M3/07
CPC分类号： G11C16/12
摘要： The present invention allows different stepped-up voltages and different output currents to be generated in one charge pump circuit without increasing the chip area of the charge pump circuit and also electric power consumption in the charge pump circuit to be reduced to a very low power consumption level in standby mode and other modes. The present invention provides a semiconductor integrated circuit device which, in one charge pump circuit with an N number of basic pump cell stages connected to step up voltages in the erase and write modes of a non-volatile memory or the like, generates stepped-up voltages lower than in the erase and write modes and different from one another in output current supply capability, by using series- or parallel-connected pump cells not in excess of the N number of pump cell stages mentioned above, and changes a voltage step-up clock to a stepped-up voltage detection signal.
摘要翻译：本发明允许在一个电荷泵电路中产生不同的升压电压和不同的输出电流，而不增加电荷泵电路的芯片面积，并且还将电荷泵电路中的电力消耗降低到非常低的功耗待机模式等模式。本发明提供了一种半导体集成电路器件，其在非易失性存储器等的擦除和写入模式下连接有N个基本泵浦单元级的一个电荷泵电路中的升压电压产生升压通过使用不超过上述N个泵浦电池级的串联或并联连接的泵浦电池，电压低于擦除和写入模式，并且输出电流供应能力彼此不同，上升时钟到升压电压检测信号。

6. 发明授权

US06590809B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US06590809B2
公开(公告)日：2003-07-08
申请号：US10040332
申请日：2002-01-09
申请人： Takanori Yamazoe , Hiroshi Yoshigi , Yoshiaki Kamigaki , Kozo Katayama , Shinichi Minami , Takeo Kanai
发明人： Takanori Yamazoe , Hiroshi Yoshigi , Yoshiaki Kamigaki , Kozo Katayama , Shinichi Minami , Takeo Kanai
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/26
摘要： When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.

7. 发明申请

US20070279191A1 RFID system 审中-公开
标题翻译： RFID系统
公开(公告)号：US20070279191A1
公开(公告)日：2007-12-06
申请号：US11802018
申请日：2007-05-18
申请人： Masaaki Yamamoto , Takanori Yamazoe , Toshiyuki Kuwana
发明人： Masaaki Yamamoto , Takanori Yamazoe , Toshiyuki Kuwana
IPC分类号： H04Q5/22
CPC分类号： H04B5/02 , G06K7/0008 , G06K7/10316 , G06K7/10356 , G06K7/10435 , H04B5/0056 , H04B5/0062
摘要： A technique of reducing the interference wave occurred between a plurality of reader/writers in an environment in which a plurality of RFID systems are operating. An RFID system includes a plurality of reader/writers and a controller for controlling the plurality of reader/writers. Each reader/writer includes a body, antennas, and a distributor for selecting one antenna from the antennas. The controller selects an antenna having a positional relationship in which the interference wave is small from the antennas of each reader/writer, and giving a command for the antenna to the body of each reader/writer. Each reader/writer selects one antenna from the antennas based on the command from the controller and transmits a command to the RFID.
摘要翻译：在多个RFID系统正在工作的环境中，在多个读取器/写入器之间发生减少干扰波的技术。 RFID系统包括多个读取器/写入器和用于控制多个读取器/写入器的控制器。每个读取器/写入器包括从天线选择一个天线的主体，天线和分配器。控制器从每个读取器/写入器的天线中选择具有干扰波小的位置关系的天线，并且向每个读取器/写入器的主体给出天线的命令。每个读取器/写入器根据来自控制器的命令从天线中选择一个天线，并向RFID发送命令。

8. 发明授权

US07254084B2 Data processing device 有权
公开(公告)号：US07254084B2
公开(公告)日：2007-08-07
申请号：US11138344
申请日：2005-05-27
申请人： Masaaki Terasawa , Yoshiki Kawajiri , Takanori Yamazoe
发明人： Masaaki Terasawa , Yoshiki Kawajiri , Takanori Yamazoe
IPC分类号： G11C5/14 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0466 , G11C16/08 , G11C16/10 , G11C16/32
摘要： A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

9. 发明授权

US07009890B2 Non-volatile semiconductor memory array and method of reading the same memory array 失效
公开(公告)号：US07009890B2
公开(公告)日：2006-03-07
申请号：US10317087
申请日：2002-12-12
申请人： Takanori Yamazoe , Hiroshi Yoshigi , Takeo Kanai
发明人： Takanori Yamazoe , Hiroshi Yoshigi , Takeo Kanai
IPC分类号： G11C16/00
CPC分类号： G11C16/26 , G11C16/32
摘要： A non-volatile semiconductor memory EEPROM is usually deteriorated depending on the number of times of program and erase operations and application years thereof. A read operation rate of the EEPROM is generally specified to the operation rate considering deterioration of memory and even in the case where the number of times of program and erase operations is rather small and application years are also rather small, the read operation has been conducted at the read operation rate specified considering deterioration of memory. Moreover, when deterioration of memory is advanced exceeding the specified deterioration, the read operation is now disabled in the worst case. In order to overcome such problem, the reference memories are allocated for every erase and program unit block in the EEPROM memory array, the reference memories are also programmed and erased whenever the memories in the block are erased and programmed and the read timing of memory is generated from the read timing of these reference memories. Moreover, the read timing of the reference memories is outputted as an external interface.

10. 发明申请

US20110306378A1 INFORMATION DISTRIBUTION SYSTEM, FIXED STATION, MOBILE STATION, AND INFORMATION DISTRIBUTION METHOD 审中-公开
标题翻译：信息分配系统，固定站，移动站和信息分配方法
公开(公告)号：US20110306378A1
公开(公告)日：2011-12-15
申请号：US13035747
申请日：2011-02-25
申请人： Yuki Himori , Shinichiro Fukushima , Hiroyuki Hamada , Masaaki Yamamoto , Takanori Yamazoe
发明人： Yuki Himori , Shinichiro Fukushima , Hiroyuki Hamada , Masaaki Yamamoto , Takanori Yamazoe
IPC分类号： H04B7/24
CPC分类号： H04W74/0808 , Y02D70/00
摘要： A plurality of masters continuously receives data through a specific channel to detect whether a slave exists nearby. On the other hand, the slave transmits data for a given period through the specific channel by a trigger specified by a user. A master near the slave receives the data transmitted by the slave and recognizes that the slave exists nearby. After the recognition of the slave, the master performs carrier senses on channels other than the specific channel and transmits data for a given period through a channel on which a carrier does not exist. After the transmission through the specific channel, the slave receives a plurality of channels other than the specific channel to receive the data transmitted by the master.
摘要翻译：多个主机通过特定通道连续地接收数据，以检测从站是否存在于附近。另一方面，从设备通过特定频道通过用户指定的触发器发送给定周期的数据。从站附近的主站接收从站发送的数据，并识别从站存在于附近。在对从机进行识别之后，主设备在特定信道之外的信道上执行载波侦听，并通过不存在载波的信道发送给定周期的数据。在通过特定信道的传输之后，从机接收除特定信道之外的多个信道，以接收主设备发送的数据。

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