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1. 发明授权

US08481915B2 Optical encoder 有权
标题翻译：光学编码器
公开(公告)号：US08481915B2
公开(公告)日：2013-07-09
申请号：US13069790
申请日：2011-03-23
申请人： Takanori Otsuka , Michio Nakamura , Mikiya Teraguchi
发明人： Takanori Otsuka , Michio Nakamura , Mikiya Teraguchi
IPC分类号： G01D5/34
CPC分类号： G01D7/00 , G01D5/24461 , G01D5/2448 , G01D5/347
摘要： An linear encoder includes: a scale; a light-emitting element that emits light onto the scale; a detecting head that has a light-receiving element that receives the light emitted by the light-emitting element to be reflected or transmitted by the scale; and a connector connected to the detecting head via a cable. The connector comprises a display that displays a status of the light received by the light-receiving element and a connector controller that controls the display. The connector controller includes a display controller that controls the display in accordance with the intensity of the light received by the light-receiving element.
摘要翻译：线性编码器包括：刻度; 将光发射到刻度上的发光元件; 检测头，其具有接收由所述发光元件发射的光以被所述标尺反射或透射的光接收元件; 以及通过电缆连接到检测头的连接器。连接器包括显示由光接收元件接收的光的状态的显示器和控制显示器的连接器控制器。连接器控制器包括根据由光接收元件接收的光的强度来控制显示的显示控制器。

2. 发明授权

US07432497B2 Absolute linear encoder 有权
标题翻译：绝对线性编码器
公开(公告)号：US07432497B2
公开(公告)日：2008-10-07
申请号：US11535783
申请日：2006-09-27
申请人： Seiji Sakagami , Mikiya Teraguchi
发明人： Seiji Sakagami , Mikiya Teraguchi
IPC分类号： G01D5/34 , G01D5/36 , H03M1/22 , G01B11/14 , G01B7/30
CPC分类号： G01D3/024 , G01D5/2497 , G01D5/34776
摘要： An absolute linear encoder includes a plurality of absolute scales aligned in the detection direction with absolute calibrations, a plurality of detectors for detecting the calibrations on the absolute scales, absolute position data generating portions of each scale for generating absolute position data of each detector, and a calculator for outputting an absolute position over the whole length of connected whole absolute scales adding the absolute position data of each detector and the distance between the detectors. The detectors are fixed at such intervals as to simultaneously detect the calibrations of the two absolute scales adjoining in a scale connecting section. Thus, the long absolute linear encoder which is easy to use is realized at low costs.
摘要翻译：绝对线性编码器包括以绝对校准方式在检测方向上对齐的多个绝对刻度，用于检测绝对刻度上的校准的多个检测器，用于产生每个检测器的绝对位置数据的每个刻度的绝对位置数据产生部分，以及用于输出连接的整个绝对刻度的整个长度上的绝对位置的计算器，添加每个检测器的绝对位置数据和检测器之间的距离。检测器以这样的间隔固定，以便同时检测刻度连接部分中邻接的两个绝对刻度的校准。因此，以低成本实现了易于使用的长绝对线性编码器。

3. 发明申请

US20070069117A1 ABSOLUTE LINEAR ENCODER 有权
标题翻译：绝对线性编码器
公开(公告)号：US20070069117A1
公开(公告)日：2007-03-29
申请号：US11535783
申请日：2006-09-27
申请人： Seiji Sakagami , Mikiya Teraguchi
发明人： Seiji Sakagami , Mikiya Teraguchi
IPC分类号： G01D5/34
CPC分类号： G01D3/024 , G01D5/2497 , G01D5/34776
摘要： An absolute linear encoder includes a plurality of absolute scales aligned in the detection direction with absolute calibrations, a plurality of detectors for detecting the calibrations on the absolute scales, absolute position data generating portions of each scale for generating absolute position data of each detector, and a calculator for outputting an absolute position over the whole length of connected whole absolute scales adding the absolute position data of each detector and the distance between the detectors. The detectors are fixed at such intervals as to simultaneously detect the calibrations of the two absolute scales adjoining in a scale connecting section. Thus, the long absolute linear encoder which is easy to use is realized at low costs.
摘要翻译：绝对线性编码器包括以绝对校准方式在检测方向上对齐的多个绝对刻度，用于检测绝对刻度上的校准的多个检测器，用于产生每个检测器的绝对位置数据的每个刻度的绝对位置数据产生部分，以及用于输出连接的整个绝对刻度的整个长度上的绝对位置的计算器，添加每个检测器的绝对位置数据和检测器之间的距离。检测器以这样的间隔固定，以便同时检测刻度连接部分中邻接的两个绝对刻度的校准。因此，以低成本实现了易于使用的长绝对线性编码器。

4. 发明授权

US5734688A Interpolation pulse generating device with two-step interpolation 失效
标题翻译：插补脉冲发生装置，具有两步插值
公开(公告)号：US5734688A
公开(公告)日：1998-03-31
申请号：US549143
申请日：1995-10-27
申请人： Mikiya Teraguchi , Kiyokazu Okamoto
发明人： Mikiya Teraguchi , Kiyokazu Okamoto
IPC分类号： G01D5/245 , G01D5/244 , G06F17/17 , H03M1/20 , H03M1/30 , G01B7/00
CPC分类号： H03M1/203 , G01D5/24404 , H03M1/303
摘要： Signals S.sub.j and S.sub.j-1 that are deviate from each other by a phase value of 2 .pi./M are generated by combining two sinusoidal detection signals. A reference signal .DELTA.S is generated which represents a difference between the signals S.sub.j and S.sub.j-1. An up-pulse or a down-pulse is generated every time the signal S.sub.j or S.sub.j-1 varies by .DELTA.S/n. An n-ary reversible ring counter outputs a first count value and a carry or borrow pulse by counting the up-pulse and the down-pulse, and the first count value is used to control the operation of generating the up-pulse or down-pulse. An M-ary reversible ring counter outputs a second count value by counting the carry pulse or the borrow pulse, and the second count value is used to control the operation of generating the signals S.sub.j and S.sub.j-1.
摘要翻译：通过组合两个正弦检测信号来产生彼此相差2pi / M的信号Sj和Sj-1。生成参考信号DELTA S，其表示信号Sj和Sj-1之间的差。每当信号Sj或Sj-1以DELTA S / n变化时，产生上升脉冲或下降脉冲。正弦可逆环形计数器通过对上升脉冲和下降脉冲进行计数来输出第一计数值和进位或借位脉冲，并且第一计数值用于控制产生上升脉冲或下降脉冲的操作，脉冲。 M元可逆环计数器通过对进位脉冲或借位脉冲进行计数而输出第二计数值，第二计数值用于控制产生信号Sj和Sj-1的操作。

5. 发明授权

US07116252B2 Encoder and signal adjustment method for the same 有权
标题翻译：编码器和信号调节方法相同
公开(公告)号：US07116252B2
公开(公告)日：2006-10-03
申请号：US11151286
申请日：2005-06-14
申请人： Mikiya Teraguchi
发明人： Mikiya Teraguchi
IPC分类号： H03M1/06
CPC分类号： G01D5/24452 , G01D5/24409 , G01D5/2448 , G01D5/2449
摘要： An encoder includes: a detector; an A/D converter for performing A/D conversion for a two-phase analog signal output from the detector; an error correction circuit for correcting an error of the two-phase analog signal; an interpolation circuit for performing interpolation from the corrected result of A/D conversion; a memory for storing correction data; and a central processing unit (CPU) having communication means. The result of A/D conversion of the two-phase analog signal is sent by the communication means to an external personal computer. The error of sine and cosine signals from a predetermined value is detected by the personal computer and is sent by the communication means. The encoder performs interpolation in which the error is corrected by using the received correction data. Thus, it is possible to perform signal adjustment without observing a display screen of an oscilloscope, while confirming a status of signal adjustment in a non-stepped manner. This enables optimum adjustment and confirmation to be performed, and reduces an interpolation error caused by adjustment of the encoder signal.
摘要翻译：编码器包括：检测器; A / D转换器，用于对从检测器输出的两相模拟信号进行A / D转换; 用于校正两相模拟信号的误差的纠错电路; 一个内插电路，用于根据A / D转换的校正结果进行插值; 用于存储校正数据的存储器; 以及具有通信装置的中央处理单元（CPU）。两相模拟信号的A / D转换的结果由通信装置发送到外部个人计算机。来自预定值的正弦和余弦信号的误差由个人计算机检测并由通信装置发送。编码器通过使用接收到的校正数据执行校正错误的插值。因此，在不以阶梯状态确认信号调整状态的情况下，可以不观察示波器的显示画面而进行信号调整。这使得能够进行最佳的调整和确认，并且减少由编码器信号的调整引起的插值误差。

6. 发明授权

US5907298A Interpolation circuit for encoder 失效
标题翻译：编码器插值电路
公开(公告)号：US5907298A
公开(公告)日：1999-05-25
申请号：US949620
申请日：1997-10-14
申请人： Tetsuro Kiriyama , Mikiya Teraguchi
发明人： Tetsuro Kiriyama , Mikiya Teraguchi
IPC分类号： G01D5/245 , G01D5/244 , G06F17/17 , H03M1/20 , H03M1/30 , G01D5/00
CPC分类号： H03M1/207 , G01D5/24404 , H03M1/303
摘要： An interpolation circuit of an encoder of which dynamic accuracy is improved is disclosed. The phase angle data detecting circuit 1 detects to store the phase angle data PH for each of the first clock CK1. The phase angle data PH is input to the updating circuit 2 in which the current data CNT is subtracted from the subsequent phase angle data PH so as to be updated. The differential data DX is limited within an upper limit to be added to the current data CNT. The integrating circuit 3 integrates the differential data DELTA1, whose upper limit is predetermined, by the second clock CK2 to generate the carry signal QUADEN at each timing when the integrated value leads to the period ratio of CK1 to CK2. The two-phase square wave generating circuit 5 generates two-phase square wave signals at each timing of the carry signal QUADEN. The over-speed detecting circuit 6 monitors the differential data DX to generate the over-speed alarm signal OSALM under a predetermined condition.
摘要翻译：公开了一种提高了动态精度的编码器的内插电路。相位角数据检测电路1检测存储第一时钟CK1中的每一个的相位角数据PH。相位角数据PH被输入到更新电路2，在更新电路2中，从随后的相位角数据PH中减去当前数据CNT以便更新。差分数据DX被限制在上限中以被添加到当前数据CNT。积分电路3通过第二时钟CK2将预定上限的差分数据DELTA1积分，以在积分值导致CK1〜CK2的周期比的每个定时产生进位信号QUADEN。两相方波发生电路5在进位信号QUADEN的每个定时产生两相方波信号。超速检测电路6监视差分数据DX，以在预定条件下产生超速报警信号OSALM。

7. 发明授权

US5999113A Interpolation circuit for encoder having a look-up table memory with reduced capacity 失效
标题翻译：具有减小容量的查找表存储器的编码器插值电路
公开(公告)号：US5999113A
公开(公告)日：1999-12-07
申请号：US59338
申请日：1998-04-14
申请人： Tetsuro Kiriyama , Mikiya Teraguchi
发明人： Tetsuro Kiriyama , Mikiya Teraguchi
IPC分类号： G01D5/245 , G01D5/244 , G06F17/17 , H03M1/20 , H03M1/30 , H03M1/48
CPC分类号： H03M1/207 , G01D5/24409 , H03M1/303
摘要： Output of an encoder are sampled by A/D converters 11a and 11b to be converted to N bits A-phase and B-phase digital data DA and DB. In a look-up table memory 12, reference phase angle data of phase divisions and average gradient vectors of changes in phase angle data within the phase divisions are stored, the phase divisions being addressed by the high order NU bits of data DA and DB. An arithmetic circuit 13 determines a vector inner product of an average gradient vector and phase-interpolating data represented by the low order NL bits of the data DA and DB to add the resultant to a phase angle data, thereby outputting an interpolated phase angle data.
摘要翻译：编码器的输出由A / D转换器11a和11b采样，以被转换成N位A相和B相数字数据DA和DB。在查找表存储器12中，相位分割的参考相位角数据和相位分割内的相位角数据的变化的平均梯度向量被存储，相位分割由数据DA和DB的高阶NU位寻址。算术电路13确定由数据DA和DB的低阶NL位表示的平均梯度矢量和相位插值数据的向量内积，以将结果加到相位角数据上，从而输出内插相位角数据。

8. 发明授权

US08290732B2 Absolute type linear encoder and method for adjusting position thereof 有权
标题翻译：绝对式线性编码器及其位置调整方法
公开(公告)号：US08290732B2
公开(公告)日：2012-10-16
申请号：US12726033
申请日：2010-03-17
申请人： Mikiya Teraguchi
发明人： Mikiya Teraguchi
IPC分类号： G06F19/00
CPC分类号： G01D21/00 , G01D1/00 , G01D15/00
摘要： An absolute type linear encoder includes: a scale including a plurality of tracks including a high-order and low-order tracks; and a detection head configured to detect a relative position to the scale; and a processing circuit configured to obtain the number of cycles of the low-order track by using a correction value obtained per correction pitch, the width of which is wider than the detection pitch, based on an error between tracks produced by a difference between the position of the high-order track to the detection head and the position of the low-order track thereto, output values of the high-order track and the low-order track, and a cyclic ratio of the low-order track to the high-order track, and obtain the position of the detection head to the scale based on the number of the cycles and the output value of the low-order track.
摘要翻译：绝对型线性编码器包括：包括包括高阶和低阶轨道的多个轨道的标尺; 以及检测头，被配置为检测与所述标尺的相对位置; 以及处理电路，被配置为基于由所述检测间隔之间的差产生的轨迹之间的误差，通过使用其宽度大于所述检测间距的每个校正间距获得的校正值来获得所述低轨迹的循环次数高阶轨道到检测头的位置和低阶轨道的位置，高阶轨迹和低阶轨迹的输出值以及低阶轨道到高位的循环比并且基于循环次数和低阶磁道的输出值，将检测头的位置获得到刻度。

9. 发明申请

US20050280563A1 Encoder and signal adjustment method for the same 有权
标题翻译：编码器和信号调节方法相同
公开(公告)号：US20050280563A1
公开(公告)日：2005-12-22
申请号：US11151286
申请日：2005-06-14
申请人： Mikiya Teraguchi
发明人： Mikiya Teraguchi
IPC分类号： G01B21/00 , G01D5/244 , H03M7/00
CPC分类号： G01D5/24452 , G01D5/24409 , G01D5/2448 , G01D5/2449
摘要： An encoder includes: a detector; an A/D converter for performing A/D conversion for a two-phase analog signal output from the detector; an error correction circuit for correcting an error of the two-phase analog signal; an interpolation circuit for performing interpolation from the corrected result of A/D conversion; a memory for storing correction data; and a central processing unit (CPU) having communication means. The result of A/D conversion of the two-phase analog signal is sent by the communication means to an external personal computer. The error of sine and cosine signals from a predetermined value is detected by the personal computer and is sent by the communication means. The encoder performs interpolation in which the error is corrected by using the received correction data. Thus, it is possible to perform signal adjustment without observing a display screen of an oscilloscope, while confirming a status of signal adjustment in a non-stepped manner. This enables optimum adjustment and confirmation to be performed, and reduces an interpolation error caused by adjustment of the encoder signal.
摘要翻译：编码器包括：检测器; A / D转换器，用于对从检测器输出的两相模拟信号进行A / D转换; 用于校正两相模拟信号的误差的纠错电路; 一个内插电路，用于根据A / D转换的校正结果进行插值; 用于存储校正数据的存储器; 以及具有通信装置的中央处理单元（CPU）。两相模拟信号的A / D转换的结果由通信装置发送到外部个人计算机。来自预定值的正弦和余弦信号的误差由个人计算机检测并由通信装置发送。编码器通过使用接收到的校正数据执行校正错误的插值。因此，在不以阶梯状态确认信号调整状态的情况下，可以不观察示波器的显示画面而进行信号调整。这使得能够进行最佳的调整和确认，并且减少由编码器信号的调整引起的插值误差。

10. 发明授权

US06937169B2 Data transmitting/receiving method and device for encoder 有权
标题翻译：用于编码器的数据发送/接收方法和装置
公开(公告)号：US06937169B2
公开(公告)日：2005-08-30
申请号：US10829538
申请日：2004-04-22
申请人： Mikiya Teraguchi , Masayoshi Okamoto
发明人： Mikiya Teraguchi , Masayoshi Okamoto
IPC分类号： G01D5/244 , H03M7/00 , H04B14/04
CPC分类号： G01D5/24428
摘要： When data detected by an encoder is transmitted/received in predetermined cycles in a measuring device using a sampling control system for controlling a position or a speed at predetermined time intervals, positional data is divided so as to be output with deviation data output each time. The divided positional is reconstituted so as to transmit the positional data within a control cycle.
摘要翻译：当使用用于以预定时间间隔控制位置或速度的采样控制系统在测量装置中以预定周期发送/接收数据时，将位置数据分割成每次输出偏差数据。重新分配位置，以便在控制周期内传送位置数据。

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