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1. 发明授权

US07765250B2 Data processor with internal memory structure for processing stream data 失效
标题翻译：具有用于处理流数据的内部存储器结构的数据处理器
公开(公告)号：US07765250B2
公开(公告)日：2010-07-27
申请号：US11271961
申请日：2005-11-14
申请人： Takanobu Tsunoda , Bryan Atwood , Masashi Takada , Hiroshi Tanaka
发明人： Takanobu Tsunoda , Bryan Atwood , Masashi Takada , Hiroshi Tanaka
IPC分类号： G06F7/38
CPC分类号： G06F15/16
摘要： There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.
摘要翻译：提供至少一个处理器块，其包括多个加载存储接口（801,804），多个存储体（821），具有输入端口（850）和输出端口（850）中的至少一个的输入/输出端口（860）和交叉开关（810），并且交叉开关将负载存储接口，存储体和输入/输出端口彼此连接，并且负载存储接口构成数据处理器，以便控制数据传送到记忆库。因此，实现了具有高传输吞吐量和灵活性并且有效地处理流数据的数据处理器。

2. 发明申请

US20060190701A1 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US20060190701A1
公开(公告)日：2006-08-24
申请号：US11271961
申请日：2005-11-14
申请人： Takanobu Tsunoda , Bryan Atwood , Masashi Takada , Hiroshi Tanaka
发明人： Takanobu Tsunoda , Bryan Atwood , Masashi Takada , Hiroshi Tanaka
IPC分类号： G06F15/00
CPC分类号： G06F15/16
摘要： There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.
摘要翻译：提供至少一个处理器块，其包括多个加载存储接口（801,804），多个存储体（821），具有输入端口（850）和输出端口（850）中的至少一个的输入/输出端口（860）和交叉开关（810），并且交叉开关将负载存储接口，存储体和输入/输出端口彼此连接，并且负载存储接口构成数据处理器，以便控制数据传送到记忆库。因此，实现了具有高传输吞吐量和灵活性并且有效地处理流数据的数据处理器。

3. 发明授权

US07756505B2 Semiconductor integrated circuit and a software radio device 有权
标题翻译：半导体集成电路和软件无线电设备
公开(公告)号：US07756505B2
公开(公告)日：2010-07-13
申请号：US11240618
申请日：2005-10-03
申请人： Hiroshi Tanaka , Takanobu Tsunoda , Tetsuroo Honmura , Manabu Kawabe , Masashi Takada
发明人： Hiroshi Tanaka , Takanobu Tsunoda , Tetsuroo Honmura , Manabu Kawabe , Masashi Takada
IPC分类号： H04B1/28 , H04B1/26 , H04M3/00 , H04M1/00 , G06F7/38 , G06F15/00 , G06F15/76 , G06F9/00 , G06F9/44 , H03K19/173 , H03K19/177 , H01L27/10 , H01L29/76
CPC分类号： H04B1/0003 , H04B1/406
摘要： To realize a software radio processing with a reduced circuit area by hardware and software which can process transmission and reception, or synchronization and demodulation in time division. There are provided a circuit DRC that can dynamically change a configuration with a structure that can change the configuration at a high speed, a general processor, and an interface for connection with an external device such as an AD converter or a DA converter. Software radio is realized by using a software radio chip that conducts plural different processing such as transmission and reception, or synchronization and demodulation in time division. The different processing during the radio signal processing can be conducted in time division. As a result, the software radio can be realized with a circuit of a reduced area in a software radio system that allocates regions of an FPGA to the respective processing.
摘要翻译：通过可以处理发送和接收的硬件和软件实现具有减少电路面积的软件无线电处理，或者在时间上进行同步和解调。提供了一种电路DRC，其可以以可以以高速度改变配置的结构动态地改变配置，通用处理器以及用于与诸如AD转换器或DA转换器的外部设备连接的接口。软件无线电通过使用进行多个不同处理的软件无线电芯片来实现，例如发送和接收，或者时分的同步和解调。无线电信号处理期间的不同处理可以分时进行。结果，软件无线电可以通过在分配FPGA的区域到相应处理的软件无线电系统中的减小区域的电路来实现。

4. 发明申请

US20060073804A1 Semiconductor integrated circuit and a software radio device 有权
标题翻译：半导体集成电路和软件无线电设备
公开(公告)号：US20060073804A1
公开(公告)日：2006-04-06
申请号：US11240618
申请日：2005-10-03
申请人： Hiroshi Tanaka , Takanobu Tsunoda , Tetsuroo Honmura , Manabu Kawabe , Masashi Takada
发明人： Hiroshi Tanaka , Takanobu Tsunoda , Tetsuroo Honmura , Manabu Kawabe , Masashi Takada
IPC分类号： H04B1/28
CPC分类号： H04B1/0003 , H04B1/406
摘要： To realize a software radio processing with a reduced circuit area by hardware and software which can process transmission and reception, or synchronization and demodulation in time division. There are provided a circuit DRC that can dynamically change a configuration with a structure that can change the configuration at a high speed, a general processor, and an interface for connection with an external device such as an AD converter or a DA converter. Software radio is realized by using a software radio chip that conducts plural different processing such as transmission and reception, or synchronization and demodulation in time division. The different processing during the radio signal processing can be conducted in time division. As a result, the software radio can be realized with a circuit of a reduced area in a software radio system that allocates regions of an FPGA to the respective processing.
摘要翻译：通过可以处理发送和接收的硬件和软件实现具有减少电路面积的软件无线电处理，或者在时间上进行同步和解调。提供了一种电路DRC，其可以以可以以高速度改变配置的结构动态地改变配置，通用处理器和用于与诸如AD转换器或DA转换器的外部设备连接的接口。软件无线电通过使用进行多个不同处理的软件无线电芯片来实现，例如发送和接收，或者时分的同步和解调。无线电信号处理期间的不同处理可以分时进行。结果，软件无线电可以通过在分配FPGA的区域到相应处理的软件无线电系统中的减小区域的电路来实现。

5. 发明申请

US20060225139A1 Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20060225139A1
公开(公告)日：2006-10-05
申请号：US11393833
申请日：2006-03-31
申请人： Masashi Takada , Takanobu Tsunoda , Hiroshi Tanaka
发明人： Masashi Takada , Takanobu Tsunoda , Hiroshi Tanaka
IPC分类号： H04L9/32 , G06F12/14 , G06F17/30 , G06F7/04 , G06F11/30 , G06K9/00 , H03M1/68 , H04K1/00 , H04L9/00 , H04N7/16
CPC分类号： G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： In a dynamic reconfigurable processor, a mechanism for effectively storing configuration data with a small hardware scale and improving processing performance is provided. Also, a sequence mechanism that is easy to be implemented with flexibility and a high operating frequency being both achieved is provided. The configuration data is hierarchically stored, and without suspending a process in a processing unit, configuration data required for subsequent processing is transferred in advance from a first storage area to a second storage area. Also, with a plurality of sequence modes, a condition determination process is performed on different sequence conditions.
摘要翻译：在动态可重构处理器中，提供了用于有效地存储具有小硬件规模的配置数据并提高处理性能的机制。此外，提供了容易实现的顺序机制，其灵活性和高操作频率都被实现。配置数据被分层存储，并且在处理单元中不中止处理的情况下，将后续处理所需的配置数据预先从第一存储区域传送到第二存储区域。此外，利用多个序列模式，对不同的序列条件执行条件确定处理。

6. 发明申请

US20060101232A1 Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20060101232A1
公开(公告)日：2006-05-11
申请号：US11240549
申请日：2005-10-03
申请人： Masashi Takada , Takanobu Tsunoda , Hiroshi Tanaka , Tetsuroo Honmura
发明人： Masashi Takada , Takanobu Tsunoda , Hiroshi Tanaka , Tetsuroo Honmura
IPC分类号： G06F15/00
CPC分类号： G06F9/3879 , G06F15/7867
摘要： The present invention relates to data access to a built-in memory or a peripheral circuit from any of ALU cells provided in the array state, and provides a semiconductor integrated circuit having an access mechanism enabling size reduction in the hardware scale and improvement in the usability. There are provided dedicated cell groups 1304, 1306 for executing memory access processing to built-in memories 1313, 1312 in a plurality of ALU cells. Further there are provided dedicated cell groups 1304, 1306 enabling access commonly available for built-in memories to a peripheral circuit 1201 or LSI external device 206. By providing dedicated cell groups for memory access processing to built-in memories, the ALU cell does not require a memory access mechanism, which enables reduction of an area and improvement in efficiency in use. Further access common to the built-in memories or peripheral circuits is possible, which enables improvement in the usability.
摘要翻译：本发明涉及从阵列状态中提供的任何一个ALU单元到内置存储器或外围电路的数据访问，并且提供了一种半导体集成电路，其具有能够缩小硬件尺寸并提高可用性的访问机构。提供了用于对多个ALU单元中的内置存储器1313,1312执行存储器访问处理的专用单元组1304,1306。此外，还提供了专用单元组1304,1306，使外部电路1201或LSI外部设备206的内置存储器通用。通过为内置存储器提供用于存储器访问处理的专用单元组，ALU单元不需要存储器访问机制，这使得能够减少面积并提高使用效率。内置存储器或外围电路通用的进一步访问是可能的，这样可以改善可用性。

7. 发明申请

US20070162529A1 Dynamically reconfigurable processor and processor control program for controlling the same 失效
标题翻译：动态可重构处理器和处理器控制程序控制相同
公开(公告)号：US20070162529A1
公开(公告)日：2007-07-12
申请号：US11593542
申请日：2006-11-07
申请人： Makoto Sato , Takanobu Tsunoda , Masashi Takada
发明人： Makoto Sato , Takanobu Tsunoda , Masashi Takada
IPC分类号： G06J1/00
CPC分类号： G06F15/8007 , G06F15/7867
摘要： A dynamically reconfigurable processor having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area is provided. The dynamically reconfigurable processor comprises: a first arithmetic circuit group composed of arithmetic circuits of a type Ai (i=1, 2, . . . , N); a second arithmetic circuit group composed of a part of an arithmetic circuit group included in the first arithmetic circuit group and an arithmetic circuit group of a type B which is connected thereto and different from the arithmetic circuit of the type Ai; inter-arithmetic-circuit wires mutually connecting the arithmetic circuits of the type Ai and the arithmetic circuits of the type B; and a switch group which causes the inter-arithmetic-circuit wires in the second arithmetic circuit group to be inter-arithmetic-circuit wires different from other inter-arithmetic-circuit wires and changes the connection order between the arithmetic circuits in the second arithmetic circuit group.
摘要翻译：提供一种具有布线结构的动态可重构处理器，其能够以小布线区域灵活地将程序映射到处理器。该动态可重构处理器包括：由类型Ai（i = 1,2，...，N）的运算电路组成的第一运算电路组; 由第一运算电路组中包括的算术电路组的一部分和与该类型的运算电路不同的类型B的运算电路组组成的第二运算电路组; 将类型Ai的运算电路和B型运算电路相互连接的运算间电路布线; 以及使第二运算电路组中的运算电路布线之间的运算电路布线与其他算术电路布线不同的开关组，并且改变第二运算电路中的运算电路之间的连接顺序组。

8. 发明授权

US07571198B2 Dynamically reconfigurable processor and processor control program for controlling the same 失效
标题翻译：动态可重构处理器和处理器控制程序控制相同
公开(公告)号：US07571198B2
公开(公告)日：2009-08-04
申请号：US11593542
申请日：2006-11-07
申请人： Makoto Sato , Takanobu Tsunoda , Masashi Takada
发明人： Makoto Sato , Takanobu Tsunoda , Masashi Takada
IPC分类号： G06F7/38
CPC分类号： G06F15/8007 , G06F15/7867
摘要： A dynamically reconfigurable processor is provided having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area. A first wire permits a first arrangement of circuit blocks and a second wire provided for changing the arrangement order of the circuit blocks. A switch is provided to switch between the first wire and the second wire. By virtue of this arrangement, a greater variety of calculations can be performed in the circuit without the necessity for increasing the number of operation blocks.
摘要翻译：提供了具有布线结构的动态可重构处理器，其能够以小的布线区域灵活地将程序映射到处理器。第一线允许电路块的第一布置和用于改变电路块的布置顺序的第二布线。提供开关以在第一线和第二线之间切换。通过这种布置，可以在电路中执行更多种类的计算，而不需要增加操作块的数量。

9. 发明申请

US20130089147A1 Video Transfer System 有权
标题翻译：视频传输系统
公开(公告)号：US20130089147A1
公开(公告)日：2013-04-11
申请号：US13703108
申请日：2011-05-20
申请人： Kazutaka Izumi , Eiko Sone , Yu Ito , Masashi Takada
发明人： Kazutaka Izumi , Eiko Sone , Yu Ito , Masashi Takada
IPC分类号： H04N7/32
CPC分类号： H04N7/32 , H04N21/4307
摘要： A synchronization signal generator of a decoder adds a predetermined value to a time value, and outputs a synchronization signal when the added time value coincides with a reproducing time value in a frame.
摘要翻译：解码器的同步信号发生器将预定值与时间值相加，并且当相加时间值与帧中的再现时间值一致时，输出同步信号。

10. 发明授权

US08090093B2 Echo canceller 有权
标题翻译：回音消除器
公开(公告)号：US08090093B2
公开(公告)日：2012-01-03
申请号：US11988005
申请日：2006-12-20
申请人： Hiromi Aoyagi , Masashi Takada
发明人： Hiromi Aoyagi , Masashi Takada
IPC分类号： H04M9/08 , H04B1/38 , A61F11/06
CPC分类号： H04M9/082 , H04B3/23
摘要： An echo canceller which can respond to a sudden change in echo characteristics in real time and does not require an alteration outside the echo canceller, includes a smoothed sending-speech signal calculation means for calculating a smoothed sending-speech signal from the sending-speech signal, the smoothed sending-speech signal being obtained by smoothing the sending-speech signal; a smoothed receiving-speech signal calculation means for calculating a smoothed receiving-speech signal from the receiving-speech signal, the smoothed receiving-speech signal being obtained by smoothing the receiving-speech signal; a delay time information generation means for obtaining delay time information reflecting delay characteristics of an echo path in accordance with a correlation between the smoothed sending-speech signal and the smoothed receiving-speech signal; and an update information generation means for obtaining update information indicating execution or suspension of updating of the tap coefficients of the adaptive filter, in accordance with the sending-speech signal, the receiving-speech signal, and the delay time information.
摘要翻译：可以实时响应回波特性的突然变化并且不需要在回波消除器之外的改变的回波消除器包括平滑的发送语音信号计算装置，用于从发送语音信号计算平滑的发送语音信号通过平滑发送语音信号获得平滑的发送语音信号; 平滑化的接收语音信号计算装置，用于从接收语音信号计算平滑的接收语音信号，平滑的接收语音信号是通过平滑接收语音信号获得的; 延迟时间信息产生装置，用于根据平滑的发送语音信号和平滑的接收语音信号之间的相关性获得反映回波路径的延迟特性的延迟时间信息; 以及更新信息产生装置，用于根据发送语音信号，接收语音信号和延迟时间信息获得指示执行或停止更新自适应滤波器的抽头系数的更新信息。

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