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1. 发明授权

US4930002A Multi-chip module structure 失效
标题翻译：多芯片模块结构
公开(公告)号：US4930002A
公开(公告)日：1990-05-29
申请号：US171770
申请日：1988-03-22
申请人： Takaji Takenaka , Tositada Netsu , Hidetaka Shigi , Masakazu Yamamoto
发明人： Takaji Takenaka , Tositada Netsu , Hidetaka Shigi , Masakazu Yamamoto
IPC分类号： H01L23/498 , H01L23/538
CPC分类号： H01L23/5383 , H01L23/49827 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/01005 , H01L2924/01023 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/15312 , H01L2924/3011
摘要： In a pin grid array type multi-chip module structure comprised of a ceramic multi-layer wiring board having the top surface on which a plurality of semiconductor devices are carried, divisional board areas each having the same size are respectively allotted to individual semiconductor devices of the same type. Within respective divisional board areas, the positional relation between the array arrangement of connecting pads on the top surface for connection to the semiconductor devices and the array arrangement of I/O pins on the bottom surface of the board is so determined as to be constant. Metallized patterns inside the board which are to be connected power supply I/O pins and ground I/O pins are made constant for respective divisional board areas allotted to individual semiconductor devices of the same type.

2. 发明授权

US06305230B1 Connector and probing system 有权
标题翻译：连接器和探测系统
公开(公告)号：US06305230B1
公开(公告)日：2001-10-23
申请号：US09423385
申请日：1999-11-08
申请人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
发明人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
IPC分类号： G01L100
CPC分类号： G01R31/2889 , G01R1/06744 , G01R1/06772 , G01R1/0735 , G01R3/00 , G01R31/2863
摘要： A connection device and test system is capable of stable, low load damage-free probing of devices under test, which have many pins with a narrow pitch. Furthermore in order to achieve high speed exchange of electrical signals or so-called high frequency electrical signals, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film, a contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member, and a compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.
摘要翻译：一个连接装置和测试系统能够稳定的，低负载的无损探测被测器件，其具有许多具有窄间距的引脚。此外，为了实现电信号的高速交换或所谓的高频电信号，提供支撑构件以支撑连接装置，多个尖端接触端子排列在探测侧的区域中，多层膜具有电连接到接触端子的多个引出线和包围绝缘层的接地层，并且框架被夹在多层膜的后侧。夹持构件设置在框架上以使多层膜突出以消除多层膜中的松弛，提供接触压力装置，用于使接触端子的顶端与来自支撑构件的预定接触压力接触每个电极并且提供顺从机构，使得尖端表面的接触端子组与电极组端子表面平行排列，使得接触端子的尖端以等压接触电极的表面。

3. 发明授权

US07285430B2 Connection device and test system 失效
标题翻译：连接设备和测试系统
公开(公告)号：US07285430B2
公开(公告)日：2007-10-23
申请号：US10873168
申请日：2004-06-23
申请人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
发明人： Susumu Kasukabe , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
IPC分类号： G01R31/26
CPC分类号： G01R31/2889 , G01R1/06744 , G01R1/06772 , G01R1/0735 , G01R3/00 , G01R31/2863
摘要： To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.
摘要翻译：为了在连接装置和测试器之间实现电信号的高速交换，提供了一种用于支撑连接装置的支撑构件，多个尖端接触端子被排列在探测侧的区域中，提供了一种多层膜，其具有电连接到接触端子的多个引出线和包围绝缘层的接地层，并且框架被夹持在多人膜的后侧。夹持构件设置在框架上以使多人影片投射出来以消除多人影片中的松弛。提供接触压力装置，用于使接触端子的尖端以预定的从支撑构件到夹紧构件的接触压力接触每个电极。提供了一种符合机构，使得尖端表面的接触端子组与电极组端子表面平行地排列，使得接触端子的尖端以相等的压力接触电极的表面。

4. 发明授权

US06197603B1 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step 失效
标题翻译：半导体器件及其制造方法，包括探针测试步骤和老化测试步骤
公开(公告)号：US06197603B1
公开(公告)日：2001-03-06
申请号：US09157153
申请日：1998-09-18
申请人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
发明人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
IPC分类号： G01R3126
CPC分类号： G01R3/00 , G01R1/0735
摘要： Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.
摘要翻译：即使当大量区域中的多个探针通过将设置在膜中的探针压在晶片上时，通过将压力负载施加到多个位置的平面上的多个位置，负载的分散也可以保持在预定容限内在探针测试步骤中与晶片相对的一侧的压力构件，代表典型的半导体器件制造步骤的老化测试步骤。因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

5. 发明授权

US6124553A Multilayer wiring board having vent holes and method of making 失效
标题翻译：具有排气孔的多层接线板及其制造方法
公开(公告)号：US6124553A
公开(公告)日：2000-09-26
申请号：US262270
申请日：1994-06-20
申请人： Yasunori Narizuka , Naoki Matsushima , Hidetaka Shigi , Haruhiko Matsuyama
发明人： Yasunori Narizuka , Naoki Matsushima , Hidetaka Shigi , Haruhiko Matsuyama
IPC分类号： H05K3/46 , H01L23/02 , H01L23/12 , H01L23/498 , H05K1/16
CPC分类号： H01L23/49838 , H01L23/49822 , H01L23/49833 , H01L2224/16 , H01L2924/00014 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/16152 , H01L2924/3025
摘要： A multilayer wiring system for preventing the generation of fixing failure due to an organic residue, eliminating an increase in the number of processes and reducing an area necessary for bonding of the cap and its fabrication method. The multilayer wiring board includes at least one wiring layer made of a conductor, at least one insulating layer made of an organic matter and a board. The wiring layer and the insulating layer are alternately laminated on the board and a cap is provided for covering the insulating layer and the wiring layer. The wiring layer has a wiring pattern for forming a wiring and a frame pattern for surrounding the wiring pattern. This frame pattern includes vent holes. The insulating layer has a shield structure made of an inorganic matter around the outer peripheral portion thereof and/or in the interior thereof. The shield structure is formed of the frame patterns continuously connected to each other and the cap is joined to an uppermost layer of the shield structure.
摘要翻译：一种用于防止由于有机残渣产生固定故障的多层布线系统，消除了工艺数量的增加并减少了盖子接合所需的面积及其制造方法。多层布线基板包括至少一层由导体制成的布线层，至少一层由有机物制成的绝缘层和基板。布线层和绝缘层交替地层叠在基板上，并且设置盖以覆盖绝缘层和布线层。布线层具有用于形成布线的布线图形和用于围绕布线图案的框图案。该框架图案包括通气孔。绝缘层具有由外周部分和/或其内部的无机物构成的屏蔽结构。屏蔽结构由彼此连续连接的框架图案形成，并且盖与屏蔽结构的最上层接合。

6. 发明申请

US20090209053A1 CONNECTION DEVICE AND TEST SYSTEM 审中-公开
标题翻译：连接装置和测试系统
公开(公告)号：US20090209053A1
公开(公告)日：2009-08-20
申请号：US12408000
申请日：2009-03-20
申请人： Susumu KASUKABE , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
发明人： Susumu KASUKABE , Terutaka Mori , Akihiko Ariga , Hidetaka Shigi , Takayoshi Watanabe , Ryuji Kono
IPC分类号： H01L21/66
CPC分类号： G01R31/2889 , G01R1/06744 , G01R1/06772 , G01R1/0735 , G01R3/00 , G01R31/2863
摘要： To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.
摘要翻译：为了在连接装置和测试器之间实现电信号的高速交换，提供支撑构件以支撑连接装置，多个尖端接触端子排列在探测侧的区域中，提供多层膜，其具有电连接到接触端子的多个引出线和包围绝缘层的接地层，并且框架被夹持在多层膜的后侧。在框架上设置夹紧构件以使多层膜突出以消除多层膜中的松弛。提供接触压力装置，用于使接触端子的尖端以预定的从支撑构件到夹紧构件的接触压力接触每个电极。提供了一种符合机构，使得尖端表面的接触端子组与电极组端子表面平行地排列，使得接触端子的尖端以相等的压力接触电极的表面。

7. 发明授权

US06455335B1 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step 失效
公开(公告)号：US06455335B1
公开(公告)日：2002-09-24
申请号：US09653624
申请日：2000-08-31
申请人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
发明人： Ryuji Kohno , Tetsuo Kumazawa , Makoto Kitano , Akihiko Ariga , Yuji Wada , Naoto Ban , Shuji Shibuya , Yasuhiro Motoyama , Kunio Matsumoto , Susumu Kasukabe , Terutaka Mori , Hidetaka Shigi , Takayoshi Watanabe
IPC分类号： G01R3126
CPC分类号： G01R3/00 , G01R1/0735
摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

8. 发明授权

US5868949A Metalization structure and manufacturing method thereof 失效
标题翻译：金属化结构及其制造方法
公开(公告)号：US5868949A
公开(公告)日：1999-02-09
申请号：US557320
申请日：1995-11-14
申请人： Hideo Sotokawa , Masashi Nishiki , Eiji Matsuzaki , Hidetaka Shigi , Toshio Terouchi , Mamoru Ogihara , Haruhiko Matsuyama , Minoru Tanaka
发明人： Hideo Sotokawa , Masashi Nishiki , Eiji Matsuzaki , Hidetaka Shigi , Toshio Terouchi , Mamoru Ogihara , Haruhiko Matsuyama , Minoru Tanaka
IPC分类号： C08G73/10 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/46 , B44C1/22
CPC分类号： H05K1/112 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K2201/0154 , H05K2201/09472 , H05K2201/09509 , H05K2201/096 , H05K2201/10674 , H05K3/4605 , Y10T428/24917
摘要： A metalization structure having a first conductor layer on the surface of an underlying layer and, further, a second conductor layer connected conductively with the first conductor layer in which a polyimide insulative film of low thermal expansion coefficient is present between at least an end of a pattern of the second conductor layer and the first conductor layer, for stably obtaining a metalization structure of high reliability and free from the worry of peeling of the conductor portion from a substrate or occurrence of cracking to the underlying layer.
摘要翻译：一种金属化结构，其具有在下层的表面上的第一导体层，并且还具有与第一导体层导电连接的第二导体层，其中热膨胀系数低的聚酰亚胺绝缘膜存在于第一导体层的至少一端第二导体层和第一导体层的图案，用于稳定地获得高可靠性的金属化结构，并且不会导致导体部分从基板剥离或者发生开裂到下层。

9. 发明授权

US5753372A Wiring structures and method of manufacturing the same 失效
标题翻译：接线结构及其制造方法
公开(公告)号：US5753372A
公开(公告)日：1998-05-19
申请号：US500157
申请日：1995-07-10
申请人： Hideo Sotokawa , Miharu Otani , Fumio Kataoka , Fusaji Shoji , Haruhiko Matsuyama , Eiji Matsuzaki , Shogi Ikeda , Hidetaka Shigi , Tetsuya Yamazaki , Naoki Matsushima , Shirou Akamatsu
发明人： Hideo Sotokawa , Miharu Otani , Fumio Kataoka , Fusaji Shoji , Haruhiko Matsuyama , Eiji Matsuzaki , Shogi Ikeda , Hidetaka Shigi , Tetsuya Yamazaki , Naoki Matsushima , Shirou Akamatsu
IPC分类号： H01L21/312 , H01L21/3205 , H01L21/768 , H01L23/532 , H05K1/00 , H05K1/03 , H05K3/46 , B32B9/04
CPC分类号： H01L21/76801 , H01L21/312 , H01L21/32056 , H01L21/76838 , H01L23/5329 , H01L2924/0002 , H05K1/0346 , H05K3/4647 , H05K3/4676 , Y10T428/24802 , Y10T428/31504 , Y10T428/31678 , Y10T428/31721
摘要： The present invention provides the wiring structure having a wiring layer and insulation layer and the method of manufacturing the same, wherein at least a part of the wiring of said wiring layer comprises copper, and said insulation layer comprises the polyimide obtained by heating the polyimide precursor composition containing the polyimide precursor having the repeating unit which can be represented by the following general formula (Chemical formula 15). ##STR1## (In this formula, R.sup.1 is at least one type of quadrivalent organic group selected from among the Chemical formulae 16, while R.sup.2 is a bivalent organic group containing aromatic ring).
摘要翻译：本发明提供具有布线层和绝缘层的布线结构及其制造方法，其中所述布线层的布线的至少一部分包括铜，并且所述绝缘层包括通过加热聚酰亚胺前体获得的聚酰亚胺含有具有可以由以下通式表示的重复单元的聚酰亚胺前体的组合物（化学式15）。（化学式15）（化学式16）选自化学式16中的四价有机基团的类型，而R2是含有芳香环的二价有机基团）。

10. 发明授权

US5262614A Circuit board and sealing structure and methods for manufacturing the same 失效
标题翻译：电路板和密封结构及其制造方法
公开(公告)号：US5262614A
公开(公告)日：1993-11-16
申请号：US714373
申请日：1991-05-31
申请人： Kaoru Katayama , Hidetaka Shigi
发明人： Kaoru Katayama , Hidetaka Shigi
IPC分类号： H05K3/28 , H01L21/48 , H01L23/02 , H01L23/10 , H05K1/03 , H05K3/00 , H05K3/24 , B23K26/02 , B23K26/08
CPC分类号： H01L21/4846 , H01L21/481 , H05K3/0032 , H05K1/0306 , H05K2203/1383 , H05K3/0052 , H05K3/243
摘要： A circuit board is manufactured by a method having the steps of depositing a metal pattern on a ceramic board, depositing a thin layer of a high polymer material on the ceramic board formed with the metal pattern, depositing a protective layer of a high polymer material on the thin layer of the high polymer material, and directing a laser beam toward and onto the protective layer and the thin layer deposited on a plating region of the metal pattern and a cutting region of the ceramic board thereby selectively removing part of those layers. The laser beam has a wavelength range of from 150 nm to 400 nm, an energy density range of from 0.5 J/cm.sup.2 to 5.0 J/cm.sup.2, and a pulse width range of from 100 ps to 1 .mu.s.
摘要翻译：电路板通过以下步骤制造：具有以下步骤的方法：在陶瓷板上沉积金属图案，在形成有金属图案的陶瓷板上沉积高分子材料薄层，将高分子材料的保护层沉积在高分子材料的薄层，并且将激光束导向保护层和沉积在金属图案的镀覆区域上的薄层和陶瓷板的切割区域，从而选择性地去除这些层的一部分。激光束的波长范围为150nm〜400nm，能量密度范围为0.5J / cm 2〜5.0J / cm 2，脉冲宽度范围为100ps〜1μs。

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