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1. 发明授权

US5637899A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5637899A
公开(公告)日：1997-06-10
申请号：US640638
申请日：1996-05-01
申请人： Takahisa Eimori , Toshiyuki Oashi , Kenichi Shimomura
发明人： Takahisa Eimori , Toshiyuki Oashi , Kenichi Shimomura
IPC分类号： H01L21/762 , H01L21/76 , H01L21/822 , H01L27/04 , H01L27/12 , H01L29/423 , H01L29/786 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/78645 , H01L27/1203 , H01L29/42384 , H01L29/78612
摘要： An SOI-MOS transistor structure is obtained which enables prevention of a substrate floating effect, reduction of the gate capacity and the contact resistance, and connection of two or more transistors in series. A semiconductor device including this transistor includes a pair of n.sup.+ type source/drain regions and a p.sup.+ type channel potential fixing region formed by dividing an active region by a first wiring and a second wiring, and a third wiring and a fourth wiring extending from respective side portions of the wirings. Since holes stored in an effective channel region flow in the p.sup.+ type channel potential fixing region, the substrate flowing effect can be prevented. Since one region of the pair of n.sup.+ type source/drain regions is wider than the other region, the contact resistance can be decreased. Further, since the gate wirings are not connected to each other, transistors can be connected in series.
摘要翻译：可以获得SOI-MOS晶体管结构，能够防止衬底浮置效应，栅极容量和接触电阻的降低以及两个或更多个串联的晶体管的连接。包括该晶体管的半导体器件包括一对n +型源极/漏极区域和通过用第一布线和第二布线分割有源区域形成的p +型沟道电位固定区域，以及从相应的第一布线和第二布线延伸的第三布线和第四布线配线的侧面部分。由于存储在有效沟道区中的空穴在p +型沟道电位固定区中流动，所以可以防止衬底流动效应。由于一对n +型源极/漏极区域的一个区域比另一个区域宽，所以可以降低接触电阻。此外，由于栅极布线彼此不连接，所以可以串联连接晶体管。

2. 发明授权

US5850090A Dynamic semiconductor memory device on SOI substrate 失效
标题翻译： SOI衬底上的动态半导体存储器件
公开(公告)号：US5850090A
公开(公告)日：1998-12-15
申请号：US744677
申请日：1996-11-06
申请人： Toshiyuki Oashi , Takahisa Eimori
发明人： Toshiyuki Oashi , Takahisa Eimori
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/10808
摘要： In a dynamic semiconductor memory device including a thin film SOI/MOSFET having a semiconductor layer on an insulator as an active region, an "L" level potential of a memory cell transistor, which connects/disconnects a capacitor for storing data as electric charges and a bit line for reading/writing data, is set at a fixed value higher than a ground potential and lower than a power supply potential, and a substrate bias is set at the ground potential. Even if isolation is carried out by LOCOS, sub-threshold leakage current due to a parasitic MOS in the vicinity of LOCOS edge can be suppressed because the potential of a word line is lower than that of the bit line when the memory cell transistor is in a cut-off state. Therefore, a dynamic semiconductor memory device including a thin film SOI/MOSFET which is immune to disturbing refresh can be achieved.
摘要翻译：在包括在绝缘体上具有半导体层的薄膜SOI / MOSFET作为有源区的动态半导体存储器件中，存储单元晶体管的“L”电位电位连接/断开用于存储数据的电容器作为电荷，用于读/写数据的位线被设置为比接地电位高且低于电源电位的固定值，并且将衬底偏置设置为接地电位。即使由LOCOS进行隔离，由于在存储单元晶体管处于位置时，由于字线的电位低于位线的电位，所以可以抑制由LOCOS边缘附近的寄生MOS引起的次阈值漏电流截止状态。因此，可以实现具有免受干扰刷新的薄膜SOI / MOSFET的动态半导体存储器件。

3. 发明授权

US5721444A Thin-film transistor having a buried impurity region and method of fabricating the same 失效
标题翻译：具有埋入杂质区的薄膜晶体管及其制造方法
公开(公告)号：US5721444A
公开(公告)日：1998-02-24
申请号：US824550
申请日：1997-03-25
申请人： Toshiyuki Oashi , Jiro Matsufusa , Takahisa Eimori , Tadashi Nishimura
发明人： Toshiyuki Oashi , Jiro Matsufusa , Takahisa Eimori , Tadashi Nishimura
IPC分类号： H01L21/316 , H01L21/02 , H01L21/205 , H01L21/265 , H01L21/76 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/78606 , H01L29/78609
摘要： A buried insulating layer is provided in a semiconductor substrate, in a position separated from its major surface. A LOCOS isolation film is provided in the major surface of the semiconductor substrate for isolating an active region from other active regions. A thin-film transistor is provided in the active region. The thin-film transistor comprises a gate electrode which is provided on the active region with interposition of a gate insulating layer. A pair of source/drain layers are provided in the major surface of the semiconductor substrate on both sides of the gate electrode. A high-concentration impurity layer is provided in the semiconductor substrate immediately under the buried insulating layer.
摘要翻译：掩埋绝缘层设置在半导体衬底中的与其主表面分离的位置。在半导体衬底的主表面上提供了一个LOCOS隔离膜，用于将活性区域与其它活性区域隔离。在有源区域中设置薄膜晶体管。薄膜晶体管包括设置在有源区上的栅极，插入栅极绝缘层。在栅电极的两侧的半导体衬底的主表面上设置一对源极/漏极层。在掩埋绝缘层正下方的半导体衬底中设置高浓度杂质层。

4. 发明授权

US5654573A Semiconductor device having SOI structure and manufacturing method therefor 失效
标题翻译：具有SOI结构的半导体器件及其制造方法
公开(公告)号：US5654573A
公开(公告)日：1997-08-05
申请号：US740511
申请日：1996-10-30
申请人： Toshiyuki Oashi , Takahisa Eimori
发明人： Toshiyuki Oashi , Takahisa Eimori
IPC分类号： H01L21/76 , H01L21/02 , H01L21/20 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01 , H01L29/76
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78612 , H01L29/78648
摘要： A semiconductor device having an SOI structure which involves no parasitic MOS transistor and substrate floating effect and has a planar element isolation region and, a manufacturing method therefor. In the semiconductor device, a field shield gate composed of an oxide film and a field shield gate electrode is formed to be buried under an SOI layer. As a result, it is possible to prevent generation of a parasitic transistor and substrate floating effects inherent in field shield gate while obtaining a planar element isolation structure.
摘要翻译：具有SOI结构的半导体器件，其不具有寄生MOS晶体管和衬底浮置效应，并且具有平面元件隔离区域及其制造方法。在半导体装置中，形成由氧化物膜和场屏蔽栅电极构成的场屏蔽栅极，埋设在SOI层的下方。结果，可以在获得平面元件隔离结构的同时防止在场屏蔽栅极中固有的寄生晶体管和衬底浮置效应的产生。

5. 发明授权

US06740584B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06740584B2
公开(公告)日：2004-05-25
申请号：US08935786
申请日：1997-09-23
申请人： Takahisa Eimori
发明人： Takahisa Eimori
IPC分类号： H01L214763
CPC分类号： H01L27/10873 , H01L21/76804 , H01L21/76816 , H01L21/76822 , H01L21/76829 , H01L21/76832 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A lower portion of an interlayer insulating film is formed contiguous with a semiconductor wafer. The lower portion has a high impurity concentration and a high etching rate. An upper portion of an interlayer insulating film is formed over the lower portion apart from the semiconductor wafer. The upper portion has a low impurity concentration and a low etching rate. A plurality of contact holes are formed through the interlayer insulating film by anisotropic etching. The bottom portion of each contact hole is expanded by isotropic etching, and a contact is formed in the contact hole. Thus, a satisfactory contact is formed in a hole of a large aspect ratio.
摘要翻译：层间绝缘膜的下部形成为与半导体晶片相邻。下部具有高杂质浓度和高蚀刻速率。在半导体晶片之外的下部形成层间绝缘膜的上部。上部具有低杂质浓度和低蚀刻速率。通过各向异性蚀刻通过层间绝缘膜形成多个接触孔。每个接触孔的底部通过各向同性蚀刻而膨胀，并且在接触孔中形成接触。因此，在大纵横比的孔中形成令人满意的接触。

6. 发明授权

US5691551A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5691551A
公开(公告)日：1997-11-25
申请号：US746806
申请日：1996-11-18
申请人： Takahisa Eimori
发明人： Takahisa Eimori
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/68
CPC分类号： H01L27/10808
摘要： In a semiconductor memory device, pitch of bit lines is made larger than pitch of word lines, and a storage node contact is positioned in each rectangular area surrounded by the bit lines and the word lines. The distance between centers of adjacent storage node contacts and the distance between centers of a bit line contact and an adjacent storage node contact are both made larger than the pitch of word lines. By this structure, planar area per unit memory cell can be increased, registration margin between the storage node and the storage node contact can be enlarged, short-circuit between the bit line and the storage node contact is prevented, and thus a memory cell structure of high production yield and high reliability can be realized.
摘要翻译：在半导体存储器件中，位线的间距大于字线的间距，并且存储节点接点位于由位线和字线包围的每个矩形区域中。相邻存储节点触点的中心之间的距离以及位线接触的中心与相邻的存储节点触点之间的距离都大于字线的间距。通过这种结构，可以增加每单位存储单元的平面面积，可以扩大存储节点与存储节点接触点之间的配准余量，从而防止位线与存储节点接触之间的短路，从而存储单元结构可以实现高产量和高可靠性。

7. 发明授权

US5097310A Complementary semiconductor device having improved device isolating region 失效
标题翻译：具有改进的器件隔离区域的补充半导体器件
公开(公告)号：US5097310A
公开(公告)日：1992-03-17
申请号：US409379
申请日：1989-09-19
申请人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
发明人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
IPC分类号： H01L21/761 , H01L21/76 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0928
摘要： A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.CC, so that an N channel MOS transistor 101 comprising the first shield electrode 52 does not turn on and a device comprising the second shield electrode does not form a field effect transistor.
摘要翻译：具有改进的隔离装置能力的互补半导体器件包括在衬底1的主表面上彼此相邻形成的P阱3和N阱2，形成在主衬底1上的P阱8中的N型杂质层在基板的主表面上形成在N阱9中的P型杂质层，形成在基板主表面上的N阱和P阱71的接合部的N型区域，第一屏蔽电极52，其通过绝缘膜形成在基板的主表面上的N型杂质层8和N型区域71之间，形成在N型区域71和P型杂质层9之间的第二屏蔽电极51，基板的主表面通过绝缘膜。第一屏蔽电极52连接到电位VSS，第二屏蔽电极51和N型区域71连接到电位VCC，使得包括第一屏蔽电极52的N沟道MOS晶体管101不导通，包括第二屏蔽电极的装置不形成场效应晶体管。

8. 发明申请

US20060255469A1 Semiconductor device and method of fabricating the same 审中-公开
公开(公告)号：US20060255469A1
公开(公告)日：2006-11-16
申请号：US11480494
申请日：2006-07-05
申请人： Takahisa Eimori
发明人： Takahisa Eimori
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/10873 , H01L21/76804 , H01L21/76816 , H01L21/76822 , H01L21/76829 , H01L21/76832 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A lower portion of an interlayer insulating film is formed contiguous with a semiconductor wafer. The lower portion has a high impurity concentration and a high etching rate. An upper portion of an interlayer insulating film is formed over the lower portion apart from the semiconductor wafer. The upper portion has a low impurity concentration and a low etching rate. A plurality of contact holes are formed through the interlayer insulating film by anisotropic etching. The bottom portion of each contact hole is expanded by isotropic etching, and a contact is formed in the contact hole. Thus, a satisfactory contact is formed in a hole of a large aspect ratio.

9. 发明授权

US07084508B2 Semiconductor device with multiple layer insulating film 失效
标题翻译：具有多层绝缘膜的半导体器件
公开(公告)号：US07084508B2
公开(公告)日：2006-08-01
申请号：US10212708
申请日：2002-08-07
申请人： Takahisa Eimori
发明人： Takahisa Eimori
IPC分类号： H01L23/48 , H01L23/58
CPC分类号： H01L27/10873 , H01L21/76804 , H01L21/76816 , H01L21/76822 , H01L21/76829 , H01L21/76832 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A lower portion of an interlayer insulating film is formed contiguous with a semiconductor wafer. The lower portion has a high impurity concentration and a high etching rate. An upper portion of an interlayer insulating film is formed over the lower portion apart from the semiconductor wafer. The upper portion has a low impurity concentration and a low etching rate. A plurality of contact holes are formed through the interlayer insulating film by anisotropic etching. The bottom portion of each contact hole is expanded by isotropic etching, and a contact is formed in the contact hole. Thus, a satisfactory contact is formed in a hole of a large aspect ratio.
摘要翻译：层间绝缘膜的下部形成为与半导体晶片相邻。下部具有高杂质浓度和高蚀刻速率。在半导体晶片之外的下部形成层间绝缘膜的上部。上部具有低杂质浓度和低蚀刻速率。通过各向异性蚀刻通过层间绝缘膜形成多个接触孔。每个接触孔的底部通过各向同性蚀刻而膨胀，并且在接触孔中形成接触。因此，在大纵横比的孔中形成令人满意的接触。

10. 发明授权

US5543646A Field effect transistor with a shaped gate electrode 失效
标题翻译：具有形状栅电极的场效应晶体管
公开(公告)号：US5543646A
公开(公告)日：1996-08-06
申请号：US787912
申请日：1991-11-05
申请人： Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori
发明人： Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/43 , H01L29/78
CPC分类号： H01L29/66598 , H01L21/28061 , H01L21/28114 , H01L29/42376 , H01L29/6659
摘要： A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.multidot.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.
摘要翻译：场效应晶体管包括具有第一导电类型的主表面和预定杂质浓度的半导体衬底，在半导体衬底的主表面上间隔开形成的第二导电类型的杂质层和用作栅电极。杂质层构成源极区域，杂质层之间的区域限定了主表面中的沟道区域。成形导电层在沟道区域之间形成有绝缘膜。成形导电层具有上部和下部，其中上部比下部长，并且与绝缘膜相邻的下部的长度基本上等于或短于主表面处的沟道区的长度。此外，成形导电层的上部和下部由相同的基底组成形成。

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