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1. 发明授权

US06680869B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06680869B2
公开(公告)日：2004-01-20
申请号：US10120447
申请日：2002-04-12
申请人： Takahiro Sonoda , Takeshi Sakata , Sadayuki Morita , Yoshinobu Nakagome , Haruko Tadokoro , Osamu Nagashima
发明人： Takahiro Sonoda , Takeshi Sakata , Sadayuki Morita , Yoshinobu Nakagome , Haruko Tadokoro , Osamu Nagashima
IPC分类号： G11C700
CPC分类号： G11C7/1087 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C8/12
摘要： A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.
摘要翻译： DDR配置的半导体存储器件提高了毛刺抗扰性，并且提供了使用的便利。它是一种动态类型的RAM，其内部电路与时钟信号同步地被控制; 提供了一种输入电路，其中在写入操作时输入的第二时钟信号用于将响应于该信号串行输入的多个写数据写入多个第一锁存电路，并且所述第一时钟信号用于采取写入第一锁存电路的数据进入第二锁存电路，以将它们传送到输入/输出数据总线; 提供逻辑电路，以根据第一时钟信号和第二时钟信号的逻辑屏蔽在第二时钟信号结束时产生的任何噪声，并产生第三时钟信号并将其提供给第一锁存电路其将写数据输出到至少第二锁存电路的输入。

2. 发明授权

US06407963B1 Semiconductor memory device of DDR configuration having improvement in glitch immunity 有权
标题翻译：具有提高毛刺抗扰性的DDR配置的半导体存储器件
公开(公告)号：US06407963B1
公开(公告)日：2002-06-18
申请号：US09689664
申请日：2000-10-13
申请人： Takahiro Sonoda , Takeshi Sakata , Sadayuki Morita , Yoshinobu Nakagome , Haruko Tadokoro , Osamu Nagashima
发明人： Takahiro Sonoda , Takeshi Sakata , Sadayuki Morita , Yoshinobu Nakagome , Haruko Tadokoro , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1087 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C8/12
摘要： A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.
摘要翻译： DDR配置的半导体存储器件提高了毛刺抗扰性，并且提供了使用的便利。它是一种动态类型的RAM，其内部电路与时钟信号同步地被控制; 提供了一种输入电路，其中在写入操作时输入的第二时钟信号用于将响应于该信号串行输入的多个写数据写入多个第一锁存电路，并且所述第一时钟信号用于采取写入第一锁存电路的数据进入第二锁存电路，以将它们传送到输入/输出数据总线; 提供逻辑电路，以根据第一时钟信号和第二时钟信号的逻辑屏蔽在第二时钟信号结束时产生的任何噪声，并产生第三时钟信号并将其提供给第一锁存电路其将写数据输出到至少第二锁存电路的输入。

3. 发明授权

US06335901B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06335901B1
公开(公告)日：2002-01-01
申请号：US09531467
申请日：2000-03-20
申请人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
发明人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.
摘要翻译：响应于外部端子（OPT）的第一状态，SDRAM将其操作模式选择为SDR模式，从而释放已经从存储器读出的数据，以响应于由时钟产生的时钟信号再生电路具有响应于外部端子（OPT）的第二状态而比较电路的输入和输出的相位或选择为DDR模式的功能，从而释放从响应于与外部时钟信号同步的由时钟信号发生电路产生的时钟信号，存储器垫。

4. 发明授权

US06754133B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06754133B2
公开(公告)日：2004-06-22
申请号：US10231286
申请日：2002-08-30
申请人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
发明人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.
摘要翻译：响应于外部终端（OPT）的第一状态，同步动态随机存取存储器（SDRAM）的操作模式选择为单数据速率（SDR）模式，从而释放从存储器中读出的数据响应于具有比较电路的输入和输出的相位或者被选择为双倍数据速率（DDR）模式的功能的时钟再生电路产生的时钟信号响应于第二状态外部端子（OPT），从而释放已经从存储器垫读出的数据，响应于与外部时钟同步的时钟信号产生电路产生的时钟信号。在SDR模式下，数据通过SDRAM中的数据线单向传输，在DDR模式下，数据通过数据线双向传输。

5. 发明授权

US06549484B2 Semiconductor device 有权
公开(公告)号：US06549484B2
公开(公告)日：2003-04-15
申请号：US09964669
申请日：2001-09-28
申请人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
发明人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

6. 发明授权

US06339344B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06339344B1
公开(公告)日：2002-01-15
申请号：US09497280
申请日：2000-02-02
申请人： Takeshi Sakata , Hitoshi Tanaka , Osamu Nagashima , Masafumi Ohi , Sadayuki Morita
发明人： Takeshi Sakata , Hitoshi Tanaka , Osamu Nagashima , Masafumi Ohi , Sadayuki Morita
IPC分类号： H03K190175
CPC分类号： H03K19/018528
摘要： Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bias voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.
摘要翻译：接收通过外部端子馈送的输入信号的差分放大器电路通过第一开关MOSFET和第二开关MOSFET被提供第一工作电压和第二工作电压，所述第一和第二开关MOSFET由偏置电压产生电路当所述输入信号接近所述第一和第二操作电压的中心电压时，形成控制电压以使所述第一开关MOSFET或所述第二开关MOSFET导通，并将另一个断开以产生相应的输出信号，当输入信号连续地采取所述第一电压或所述第二电压预定的时间段，从而提供对应于所述第一操作电压和所述第二操作电压的第一幅度的输入信号以及对应于所述第一操作电压的第二幅度的输入信号所述第一操作电压和所述第二操作电压之间的预定中间电压工作电压。

7. 发明授权

US06483349B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06483349B2
公开(公告)日：2002-11-19
申请号：US09987531
申请日：2001-11-15
申请人： Takeshi Sakata , Hitoshi Tanaka , Osamu Nagashima , Masafumi Ohi , Sadayuki Morita
发明人： Takeshi Sakata , Hitoshi Tanaka , Osamu Nagashima , Masafumi Ohi , Sadayuki Morita
IPC分类号： A03K190175
CPC分类号： H03K19/018528
摘要： Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bis voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.
摘要翻译：接收通过外部端子馈送的输入信号的差分放大器电路通过第一开关MOSFET和第二开关MOSFET被提供第一工作电压和第二工作电压，所述第一和第二开关MOSFET由双电压发生电路当所述输入信号接近所述第一和第二操作电压的中心电压时，形成控制电压以使所述第一开关MOSFET或所述第二开关MOSFET导通，并将另一个断开以产生相应的输出信号，当输入信号连续地采取所述第一电压或所述第二电压预定的时间段，从而提供对应于所述第一操作电压和所述第二操作电压的第一幅度的输入信号以及对应于所述第一操作电压的第二幅度的输入信号所述第一操作电压和所述第二操作电压之间的预定中间电压工作电压。

8. 发明授权

US5854562A Sense amplifier circuit 失效
标题翻译：感应放大电路
公开(公告)号：US5854562A
公开(公告)日：1998-12-29
申请号：US842536
申请日：1997-04-15
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译：一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。

9. 发明授权

US06885599B2 Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device 失效
标题翻译：半导体晶片，半导体芯片和半导体器件的制造方法
公开(公告)号：US06885599B2
公开(公告)日：2005-04-26
申请号：US10764539
申请日：2004-01-27
申请人： Yoshikazu Saitoh , Sadayuki Morita , Takahiro Sonoda
发明人： Yoshikazu Saitoh , Sadayuki Morita , Takahiro Sonoda
IPC分类号： G01R31/30 , G01R31/28 , G11C29/00 , G11C29/48 , H01L21/66 , G11C7/00
CPC分类号： G11C29/48
摘要： By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.
摘要翻译：通过在老化期间使用少量的针和接触端子，在每个针与每个半导体芯片中提供的每个端子之间进行电接触检查，从而可以提高组装产品的产量。根据其中形成有易失性存储器芯片和非易失性存储器芯片的封装结构，根据在半导体晶片的状态下执行每个存储芯片的老化的生产方案，并且通过使用经过老化的良好易失性存储器芯片以及类似地，非易失性存储器芯片形成封装结构。在该老化期间，通过将设置在老化板中的针与例如在每个半导体芯片上形成的测试电路的六个测试信号端子接触来进行接触检查。

10. 发明授权

US06271687B1 Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：US06271687B1
公开(公告)日：2001-08-07
申请号：US09531530
申请日：2000-03-21
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C706
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译：一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。

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