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1. 发明申请

US20050182916A1 Processor and compiler 有权
标题翻译：处理器和编译器
公开(公告)号：US20050182916A1
公开(公告)日：2005-08-18
申请号：US10949230
申请日：2004-09-27
申请人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
发明人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
IPC分类号： G06F9/38 , G06F9/30 , G06F9/34 , G06F9/45 , G06F15/00
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/30156 , G06F9/3016 , G06F9/3822 , G06F9/3885
摘要： A VLIW processor which has an instruction set whose size is reduced so that a small number of bits are necessary to specify registers is provided. The VLIW processor 10 comprises the register file 12, the first-the third operation units 14a-14c and the like, and executes the very long instruction word. And, the very long instruction word includes the register specifying field which specifies a least one of the registers in the register file 12 and a plurality of instructions. The operand of each instruction has the bits, src1 src2 and dst, indicating whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
摘要翻译：提供了具有指令集的VLIW处理器，其大小被减小以便需要少量位来指定寄存器。 VLIW处理器10包括寄存器文件12，第一个第三操作单元14 a-14 c等，并且执行非常长的指令字。并且，长指令字包括指定寄存器文件12中的至少一个寄存器的寄存器指定字段和多个指令。每个指令的操作数都有位src 1 src 2和dst，表示由寄存器指定字段指定的寄存器是否用作源寄存器和目的寄存器。

2. 发明授权

US08738892B2 Very long instruction word (VLIW) computer having efficient instruction code format 有权
标题翻译：超长指令字（VLIW）计算机具有有效的指令码格式
公开(公告)号：US08738892B2
公开(公告)日：2014-05-27
申请号：US12103372
申请日：2008-04-15
申请人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
发明人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
IPC分类号： G06F15/00
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/30156 , G06F9/3016 , G06F9/3822 , G06F9/3885
摘要： A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
摘要翻译：具有缩小尺寸的指令集的超长指令字（VLIW）处理器，导致指定寄存器所需的少量位。 VLIW处理器包括寄存器文件和第一至第三操作单元，并且执行非常长的指令字。此外，非常长的指令字包括指定寄存器文件中的至少一个寄存器和多个指令的寄存器指定字段。每个指令的操作数包括位src1，src2和dst，它们指示由寄存器指定字段指定的寄存器是否用作源寄存器和目标寄存器。

3. 发明授权

US07383422B2 Very long instruction word (VLIW) computer having an efficient instruction code format 有权
标题翻译：非常长的指令字（VLIW）计算机具有有效的指令码格式
公开(公告)号：US07383422B2
公开(公告)日：2008-06-03
申请号：US10949230
申请日：2004-09-27
申请人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
发明人： Takahiro Kageyama , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
IPC分类号： G06F15/76
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/30156 , G06F9/3016 , G06F9/3822 , G06F9/3885
摘要： A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
摘要翻译：具有缩小尺寸的指令集的超长指令字（VLIW）处理器，导致指定寄存器所需的少量位。 VLIW处理器包括寄存器文件和第一至第三操作单元，并且执行非常长的指令字。此外，非常长的指令字包括指定寄存器文件中的至少一个寄存器和多个指令的寄存器指定字段。每个指令的操作数包括位src 1，src 2和dst，它们指示由寄存器指定字段指定的寄存器是否用作源寄存器和目标寄存器。

4. 发明申请

US20080201560A1 VERY LONG INSTRUCTION WORD (VLIW) COMPUTER HAVING EFFICIENT INSTRUCTION CODE FORMAT 有权
标题翻译：具有有效指导代码格式的非常长的指令词（VLIW）计算机
公开(公告)号：US20080201560A1
公开(公告)日：2008-08-21
申请号：US12103372
申请日：2008-04-15
申请人： Takahiro KAGEYAMA , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
发明人： Takahiro KAGEYAMA , Hideshi Nishida , Takeshi Tanaka , Kouji Nakajima
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/30156 , G06F9/3016 , G06F9/3822 , G06F9/3885
摘要： A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.
摘要翻译：具有缩小尺寸的指令集的超长指令字（VLIW）处理器，导致指定寄存器所需的少量位。 VLIW处理器包括寄存器文件和第一至第三操作单元，并且执行非常长的指令字。此外，非常长的指令字包括指定寄存器文件中的至少一个寄存器和多个指令的寄存器指定字段。每个指令的操作数包括位src 1，src 2和dst，它们指示由寄存器指定字段指定的寄存器是否用作源寄存器和目标寄存器。

5. 发明授权

US08588304B2 Video decoding device, video decoding method, video decoding program, and video decoding integrated circuit 有权
标题翻译：视频解码装置，视频解码方式，视频解码程序，视频解码集成电路
公开(公告)号：US08588304B2
公开(公告)日：2013-11-19
申请号：US11393426
申请日：2006-03-30
申请人： Hiroshi Amano , Takeshi Tanaka , Kouji Nakajima , Eiji Otomura
发明人： Hiroshi Amano , Takeshi Tanaka , Kouji Nakajima , Eiji Otomura
IPC分类号： H04N7/12
CPC分类号： H04N19/513 , H04N19/122 , H04N19/176 , H04N19/182 , H04N19/44 , H04N19/51 , H04N19/583 , H04N19/61 , H04N19/70
摘要： With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
摘要翻译：通过使用用于运动补偿的简化程序或计算装置，视频解码装置如在MPEG-4AVC标准中解码通过宏块单元上的运动检测操作压缩的视频数据。视频解码装置将规定尺寸的压缩数据块例如16×16像素分割，生成小于块的子块，视频解码装置能够执行运动补偿操作。视频解码装置复制分配给给定块的运动矢量以产生与给定块中的子块一样多的运动矢量，并且使用相应的重复运动矢量对每个子块执行运动补偿。对每个子块的运动补偿操作产生的数据进行组合以获得与给定块对应的目标块。

6. 发明申请

US20120087413A1 VIDEO DECODING DEVICE, VIDEO DECODING METHOD, VIDEO DECODING PROGRAM, AND VIDEO DECODING INTEGRATED CIRCUIT 有权
标题翻译：视频解码设备，视频解码方法，视频解码程序和视频解码集成电路
公开(公告)号：US20120087413A1
公开(公告)日：2012-04-12
申请号：US13328950
申请日：2011-12-16
申请人： Hiroshi Amano , Takeshi Tanaka , Kouji Nakajima , Eiji Otomura
发明人： Hiroshi Amano , Takeshi Tanaka , Kouji Nakajima , Eiji Otomura
IPC分类号： H04N7/36 , H04N7/26
CPC分类号： H04N19/513 , H04N19/122 , H04N19/176 , H04N19/182 , H04N19/44 , H04N19/51 , H04N19/583 , H04N19/61 , H04N19/70
摘要： With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
摘要翻译：通过使用用于运动补偿的简化程序或计算装置，视频解码装置如在MPEG-4AVC标准中解码通过宏块单元上的运动检测操作压缩的视频数据。视频解码装置将规定尺寸的压缩数据块例如16×16像素分割，生成小于块的子块，视频解码装置能够执行运动补偿操作。视频解码装置复制分配给给定块的运动矢量以产生与给定块中的子块一样多的运动矢量，并且使用相应的重复运动矢量对每个子块执行运动补偿。对每个子块的运动补偿操作产生的数据进行组合以获得与给定块对应的目标块。

7. 发明申请

US20060239354A1 Video decoding device, video decoding method, video decoding program, and video decoding integrated circuit 有权
标题翻译：视频解码装置，视频解码方式，视频解码程序，视频解码集成电路
公开(公告)号：US20060239354A1
公开(公告)日：2006-10-26
申请号：US11393426
申请日：2006-03-30
申请人： Hiroshi Amano , Takeshi Tanaka , Kouji Nakajima , Eiji Otomura
发明人： Hiroshi Amano , Takeshi Tanaka , Kouji Nakajima , Eiji Otomura
IPC分类号： H04N11/02 , H04N7/12 , H04B1/66 , H04N11/04
CPC分类号： H04N19/513 , H04N19/122 , H04N19/176 , H04N19/182 , H04N19/44 , H04N19/51 , H04N19/583 , H04N19/61 , H04N19/70
摘要： With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.
摘要翻译：通过使用用于运动补偿的简化程序或计算装置，视频解码装置如在MPEG-4AVC标准中解码通过宏块单元上的运动检测操作压缩的视频数据。视频解码装置将规定尺寸的压缩数据块例如16×16像素分割，生成小于块的子块，视频解码装置能够进行运动补偿动作。视频解码装置复制分配给给定块的运动矢量以产生与给定块中的子块一样多的运动矢量，并且使用相应的重复运动矢量对每个子块执行运动补偿。对每个子块的运动补偿操作产生的数据进行组合以获得与给定块对应的目标块。

8. 发明授权

US08654847B2 Video decoding device, video decoding method, video decoding program, and video decoding integrated circuit 有权
公开(公告)号：US08654847B2
公开(公告)日：2014-02-18
申请号：US13328950
申请日：2011-12-16
申请人： Hiroshi Amano , Takeshi Tanaka , Kouji Nakajima , Eiji Otomura
发明人： Hiroshi Amano , Takeshi Tanaka , Kouji Nakajima , Eiji Otomura
IPC分类号： H04N7/12
CPC分类号： H04N19/513 , H04N19/122 , H04N19/176 , H04N19/182 , H04N19/44 , H04N19/51 , H04N19/583 , H04N19/61 , H04N19/70
摘要： With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.

9. 发明申请

US20070052852A1 Motion picture display device 有权
标题翻译：动态影像显示装置
公开(公告)号：US20070052852A1
公开(公告)日：2007-03-08
申请号：US11513354
申请日：2006-08-31
申请人： Keisuke Yorioka , Yoshihiro Nakahara , Kouji Nakajima , Manabu Kuroda
发明人： Keisuke Yorioka , Yoshihiro Nakahara , Kouji Nakajima , Manabu Kuroda
IPC分类号： H04N5/46 , H04N9/64
CPC分类号： G09G5/393 , G09G5/18 , G09G5/395 , G09G2320/106 , H04N7/0122
摘要： An address generating unit 102 generates a different write start address (w_adr) of a picture memory 105 depending on an aspect ratio and/or a display plane position of a motion picture to be displayed. A picture writing unit 104 writes data to the picture memory 105, starting at the calculated write start address (w_adr). A picture reading unit 108 uses the write start address (w_adr) as a read start address (r_adr) and reads data from the picture memory 105, starting at the read start address (r_adr).
摘要翻译：地址生成单元102根据要显示的运动图像的宽高比和/或显示平面位置生成图片存储器105的不同的写入开始地址（w_adr）。图像写入单元104从计算出的写开始地址（w_adr）开始将数据写入图像存储器105。图像读取单元108使用写开始地址（w_adr）作为读取开始地址（r_adr），并从读取的起始地址（r_adr）开始从图片存储器105读取数据。

10. 发明授权

US06919771B2 Digital amplifier 失效
标题翻译：数字放大器
公开(公告)号：US06919771B2
公开(公告)日：2005-07-19
申请号：US10669374
申请日：2003-09-25
申请人： Kouji Nakajima
发明人： Kouji Nakajima
IPC分类号： H03F3/181 , H03F3/217 , H03F3/38 , H03G3/30 , H03G3/34 , H03K7/08 , G11B20/10
CPC分类号： H03G3/3021 , H03F3/217 , H03F2200/03 , H03F2200/351 , H03G3/341
摘要： An object of the present invention is to provide a digital amplifier which is capable of preventing a reproduction of an analogue audio signal from a loud speaker, when an output sound volume from the loud speaker is set to zero and when inputting of a digital audio signal or an input signal is stopped. In order to achieve the object, in the digital amplifier of the present invention, a silent PWM signal output section 7 outputs a PWM signal having a duty ratio of 50%, instead of a PWM signal generated by the PWM signal generating section 6, in the following cases: the factor detecting section 3 detects that the digital audio signal is multiplied by the factor “0” in the gain regulation section 2, the silent signal determining section 4 determines that the signal input from the reproducing unit 13 is stopped, and the silent signal determining section 4 determines that the digital audio signal is a signal at a silent level.
摘要翻译：本发明的目的是提供一种数字放大器，其能够防止从扬声器再现模拟音频信号，当来自扬声器的输出音量被设置为零时，并且当输入数字音频信号或输入信号停止。为了实现该目的，在本发明的数字放大器中，静音PWM信号输出部分7输出占空比为50％的PWM信号，而不是由PWM信号产生部分6产生的PWM信号以下情况：因素检测部分3检测到数字音频信号在增益调节部分2中乘以因子“0”，无声信号确定部分4确定从再现单元13输入的信号停止，以及无声信号确定部分4确定数字音频信号是静音级的信号。

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