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1. 发明授权

US5591794A Rubber composition for tire tread 失效
标题翻译：轮胎胎面橡胶组合物
公开(公告)号：US5591794A
公开(公告)日：1997-01-07
申请号：US421606
申请日：1995-04-13
申请人： Takahiro Fukumoto , Yoko Nakada , Yoichi Mizuno
发明人： Takahiro Fukumoto , Yoko Nakada , Yoichi Mizuno
IPC分类号： B60C1/00 , C08K3/34 , C08L19/00 , C08L21/00
CPC分类号： C08K3/346 , B60C1/0016 , C08L19/003 , C08L21/00 , C08L7/00 , C08L9/00
摘要： A tread rubber composition is provided which includes 100 parts by weight of a diene rubber containing as a main component thereof at least one rubber selected from the group consisting of natural rubber, polyisoprene and polybutadiene, and 30 to 90 parts by weight of a vulcanized rubber powder, wherein the vulcanized rubber powder is a powder of a rubber resulting from the vulcanization of a rubber composition including 100 parts by weight of a diene rubber containing as a main component thereof at least one rubber selected from the group consisting of natural rubber, polyisoprene and polybutadiene, and 30 to 100 parts by weight of a clay mainly composed of kaolinite. The rubber composition for tire tread assures improved braking performance with the fracture resistance thereof kept satisfactory and, hence, a tire tread made of such rubber composition makes it possible to build a studless tire exhibiting an improved gripping force.
摘要翻译：提供了一种胎面橡胶组合物，其包含100重量份的二烯橡胶，其含有选自天然橡胶，聚异戊二烯和聚丁二烯的至少一种橡胶作为其主要成分，以及30至90重量份的硫化橡胶粉末，其中所述硫化橡胶粉末是由橡胶组合物硫化得到的橡胶粉末，所述橡胶组合物包含100重量份的二烯橡胶作为主要组分，所述二烯橡胶含有至少一种选自天然橡胶，聚异戊二烯和聚丁二烯，以及30至100重量份主要由高岭石组成的粘土。用于轮胎胎面的橡胶组合物确保改进的制动性能，其耐断裂性保持令人满意，因此，由这种橡胶组合物制成的轮胎胎面使得可以构建出具有改进的夹紧力的无钉防滑轮胎。

2. 发明授权

US6147151A Tread rubber composition and tire using the composition 失效
标题翻译：轮胎橡胶组合物和轮胎使用组合物
公开(公告)号：US6147151A
公开(公告)日：2000-11-14
申请号：US345826
申请日：1994-11-21
申请人： Takahiro Fukumoto , Yoko Nakada , Yoichi Mizuno , Kazuo Kadomaru
发明人： Takahiro Fukumoto , Yoko Nakada , Yoichi Mizuno , Kazuo Kadomaru
IPC分类号： B60C1/00 , C08K3/00 , C08K3/34 , C08K5/00 , C08K5/54 , C08K9/06 , C08K13/02 , C08K13/06 , C08L21/00 , B60C11/00
CPC分类号： C08K3/346 , C08K9/06
摘要： A tread rubber composition of excellent hydrophobic property and water repellency suitable to a studless tire of excellent performance on ice, comprising a diene rubber comprising at least one rubber selected from the group consisting of natural rubber, isoprene and polybutadiene as a main ingredient and, based on 100 parts by weight of the diene rubber, from 10 to 40 parts by weight of a clay comprising kaolinite as a main ingredient and having an oil absorption amount of from 50 to 70 g/100 g and 0.1 to 8 parts by weight of a silane coupling agent.
摘要翻译：一种具有优异的疏水性和防水性的胎面橡胶组合物，其适用于在冰上具有优异性能的无钉轮胎，其包含二烯橡胶，其包含至少一种选自天然橡胶，异戊二烯和聚丁二烯作为主要成分的橡胶，基于在100重量份的二烯橡胶中，10〜40重量份的以高岭石为主要成分并且吸油量为50〜70g / 100g的粘土和0.1〜8重量份的硅烷偶联剂。

3. 发明授权

US5859142A Rubber composition for reinforcing bead of tires which contains butadiene rubber with syndiotactic crystals, carbon black, sulfur and sulfenamide accelerator 失效
标题翻译：用于增强轮胎胎圈的橡胶组合物，其包含具有间同立构晶体的丁二烯橡胶，炭黑，硫和次磺酰胺促进剂
公开(公告)号：US5859142A
公开(公告)日：1999-01-12
申请号：US313590
申请日：1994-09-29
申请人： Kiyoshige Muraoka , Yoko Nakada , Takahiro Fukumoto , Toru Iizuka , Kaoru Koyama
发明人： Kiyoshige Muraoka , Yoko Nakada , Takahiro Fukumoto , Toru Iizuka , Kaoru Koyama
IPC分类号： B60C1/00 , B60C15/06 , C08K3/04 , C08K5/43 , C08K13/02 , C08L9/00 , C08L21/00 , C08C19/20
CPC分类号： C08L7/00 , B60C15/06 , C08L9/00 , B60C2015/0614 , C08K3/04 , C08K5/44
摘要： A rubber composition suitable for reinforcing beads of tires, having high hardness, high durability and high aging resistance, which comprises a rubber component containing 30 to 70% by weight of a butadiene rubber containing syndiotactic crystals, 60 to 75 parts by weight of a carbon black having a specified iodine adsorption number and a specified oil absorption, 1 to 2 parts by weight of sulfur and 2 to 4 parts by weight of a sulfenamide accelerator, respectively, per 100 parts by weight of the rubber component, wherein the total amount of sulfur and the sulfenamide accelerator is from 3 to 5 parts by weight.
摘要翻译：一种适用于增强具有高硬度，高耐久性和高耐老化性的轮胎胎圈的橡胶组合物，其包含含有30至70重量％的含有间同立构晶体的丁二烯橡胶的橡胶组分，60至75重量份的碳相对于100重量份的橡胶成分，分别具有规定的碘吸附数和规定的吸油量的黑色，1〜2重量份的硫和2〜4重量份的亚磺酰胺促进剂，其中，硫和次磺酰胺促进剂为3至5重量份。

4. 发明授权

US5625212A Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5625212A
公开(公告)日：1997-04-29
申请号：US445925
申请日：1995-05-22
申请人： Takahiro Fukumoto
发明人： Takahiro Fukumoto
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , H01L29/7883
摘要： On a semiconductor substrate, a floating gate electrode composed of a first layer of polysilicon is disposed through a gate dielectric film, and the drain diffusion layer contacts with the floating gate electrode by self-alignment.. The source diffusion layer is disposed to have an offset. The control gate electrode is formed through the ON film and second gate dielectric film on the floating gate electrode. The control gate electrode is formed to cover the offset region. The first gale dielectric film is formed entirely of the tunneling dielectric film at least in the region beneath the floating gate electrode. In such constitution, an electrically erasable and programmable semiconductor memory device small in cell area and excellent in matching with other process may be obtained.
摘要翻译：在半导体衬底上，通过栅极电介质膜设置由第一多晶硅层构成的浮置栅极，并且漏极扩散层通过自对准与浮置栅电极接触。源极扩散层被设置为具有抵消。控制栅电极通过浮栅电极上的导通膜和第二栅极电介质膜形成。控制栅电极形成为覆盖偏移区域。至少在浮栅电极下方的区域，第一高频电介质膜完全由隧道电介质膜形成。在这种结构中，可以获得小单元区域的电可擦除和可编程的半导体存储器件，并且可以获得与其它工艺匹配的优异。

5. 发明授权

US5367185A Non-volatile semiconductor memory with third electrode covering control gate 失效
标题翻译：具有第三电极覆盖控制栅极的非易失性半导体存储器
公开(公告)号：US5367185A
公开(公告)日：1994-11-22
申请号：US000555
申请日：1993-01-04
申请人： Takahiro Fukumoto
发明人： Takahiro Fukumoto
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/78
CPC分类号： H01L29/42324 , H01L29/66825 , H01L29/7884 , H01L27/115
摘要： A non-volatile semiconductor memory including a semiconductor substrate, drain and source regions which are provided on the surface of the semiconductor substrate and have P or N type differently from the semiconductor substrate, a floating gate (first gate electrode) for covering a portion of a channel region between the drain and source regions, the drain region being self-aligned with the floating gate, the source region being provided apart from the floating gate through an offset region in the channel region by a constant distance, whereby the drain and source regions are asymmetrical to each other through the floating gate, a control gate (second gate electrode) for controlling the surface potential of the whole channel region, and a third gate electrode provided above the control gate through an insulating film for substantially controlling the surface potential on the underside of the floating gate and in the vicinity thereof so that electrical writing and erasure can be performed, wherein the density of the offset region on the semiconductor substrate surface is made different from that of other portions on the semiconductor substrate surface so that electrons can be injected from a source.
摘要翻译：一种非易失性半导体存储器，包括半导体衬底，漏极和源极区域，其设置在半导体衬底的表面上并且具有与半导体衬底不同的P或N型，用于覆盖半导体衬底的一部分的浮置栅极（第一栅电极）在漏极和源极区之间的沟道区域，所述漏极区域与所述浮置栅极自对准，所述源极区域通过所述沟道区域中的偏移区域与所述浮动栅极分开设置一定距离，由此所述漏极和源极区域通过浮置栅极彼此不对称，用于控制整个沟道区域的表面电位的控制栅极（第二栅电极）和通过绝缘膜设置在控制栅极上方的用于基本控制表面电位的第三栅电极在浮动门的下侧及其附近，可以实现电气写入和擦除 med，其中半导体衬底表面上的偏移区域的密度与半导体衬底表面上的其它部分的密度不同，使得可以从源注入电子。

6. 发明授权

US5994184A Semiconductor memory device and method of manufacturing the same 失效
公开(公告)号：US5994184A
公开(公告)日：1999-11-30
申请号：US884874
申请日：1997-06-30
申请人： Takahiro Fukumoto
发明人： Takahiro Fukumoto
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , H01L29/7883
摘要： On a semiconductor substrate, a floating gate electrode composed of a first layer of polysilicon is disposed through a gate dielectric film, and the drain diffusion layer contacts with the floating gate electrode by self-alignment. The source diffusion layer is disposed to have an offset. The control gate electrode is formed through the ON film and second gate dielectric film on the floating gate electrode. The control gate electrode is formed to cover the offset region. The first gate dielectric film is formed entirely of the tunneling dielectric film at least in the region beneath the floating gate electrode. In such constitution, an electrically erasable and programmable semiconductor memory device small in cell area and excellent in matching with other process may be obtained.

7. 发明授权

US5394360A Non-volatile large capacity high speed memory with electron injection from a source into a floating gate 失效
标题翻译：非易失性大容量高速存储器，从源极进入电子注入浮栅
公开(公告)号：US5394360A
公开(公告)日：1995-02-28
申请号：US77953
申请日：1993-06-18
申请人： Takahiro Fukumoto
发明人： Takahiro Fukumoto
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： H01L29/7885
摘要： A non-volatile semiconductor memory providing a semiconductor substrate, drain and source regions which are provided on the surface of the semiconductor substrate and have a conductivity type different from that of the semiconductor substrate, a channel region formed between the drain and source regions, a floating gate (first gate electrode) for covering a part of the channel region. The drain region is self-aligned with the floating gate, and the source region is offset from the floating gate through an offset region by a constant distance. As a result, the drain and source regions are located asymmetrically with respect to the floating gate. A control gate (second gate electrode) substantially controls the surface potentials on the underside and in the vicinity of the floating gate. A selection gate (third gate electrode) controls the surface potential of the whole channel region including the offset region. The control gate as the second gate electrode is directly capacitively-coupled with the floating gate wholly (or partially) in portions other than the offset region. The selection gate is the third gate electrode is provided above the control gate and the floating gate so as to overlap with the control gate over all of the channel region, whereby electrons are injected from the source region to permit electrical writing and erasure.
摘要翻译：一种非易失性半导体存储器，其提供半导体衬底，漏极和源极区域，其设置在半导体衬底的表面上并且具有与半导体衬底不同的导电类型，形成在漏极和源极区域之间的沟道区域，浮栅（第一栅电极），用于覆盖沟道区的一部分。漏极区域与浮动栅极自对准，并且源极区域通过偏移区域从浮动栅极偏移恒定的距离。结果，漏极和源极区域相对于浮动栅极不对称地定位。控制栅极（第二栅电极）基本上控制下侧和浮栅附近的表面电位。选择栅极（第三栅电极）控制包括偏移区域的整个沟道区域的表面电位。作为第二栅电极的控制栅极与除偏移区域以外的部分完全（或部分地）与浮置栅极直接电容耦合。选择栅极是设置在控制栅极和浮置栅极上方的第三栅电极，以便在所有沟道区域上与控制栅极重叠，从而从源极区域注入电子以允许电写入和擦除。

8. 发明授权

US06699753B2 Method of fabricating an array of non-volatile memory cells 有权
标题翻译：制造非易失性存储单元阵列的方法
公开(公告)号：US06699753B2
公开(公告)日：2004-03-02
申请号：US10197958
申请日：2002-07-16
申请人： Yueh Yale Ma , Takahiro Fukumoto
发明人： Yueh Yale Ma , Takahiro Fukumoto
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , Y10S257/90
摘要： A method of fabricating a contact-less array of non-volatile memory cells includes: (A) forming over the substrate three stacks S1, S2 and S3 of first and second polysilicon layers; (B) forming in the substrate a drain region between the stacks S1 and S2, self-aligned to the edges of stacks S1 and S2, (C) forming side-wall spacers adjacent to edges of each polysilicon stack, (D) forming in the substrate a source region between stacks S2 and S3, self-aligned to the side-wall spacers; (E) forming a composite layer of HTO-Nitride-Polysilicon (ONP) over the array of memory cells immediately after step (B); (F) converting the ONP composite layer to ONO composite layer after step (D); (G) anisotropically etching the ONO composite layer to form ONO side-wall spacers adjacent to edges of the polysilicon stacks; and (H) growing select gate oxide over the row of polysilicon.
摘要翻译：制造非易失性存储单元的无接触阵列的方法包括：（A）在衬底上形成第一和第二多晶硅层的三个堆叠S1，S2和S3; （B）在衬底中形成与堆叠S1和S2的边缘自对准的堆叠S1和S2之间的漏极区域，（C）形成邻近每个多晶硅堆叠边缘的侧壁间隔物（D），形成在衬底是堆叠S2和S3之间的源区域，与侧壁间隔物自对准; （E）在步骤（B）之后立即在存储单元阵列上形成HTO-氮化物 - 多晶硅（ONP）的复合层; （F）在步骤（D）之后将ONP复合层转化为ONO复合层; （G）各向异性蚀刻ONO复合层以形成邻近多晶硅堆叠边缘的ONO侧壁间隔物; 和（H）在多晶硅行上生长选择栅极氧化物。

9. 发明授权

US5753953A Semiconductor storage device and method of driving the same 失效
标题翻译：半导体存储装置及其驱动方法
公开(公告)号：US5753953A
公开(公告)日：1998-05-19
申请号：US709901
申请日：1996-09-09
申请人： Takahiro Fukumoto
发明人： Takahiro Fukumoto
IPC分类号： G11C16/04 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L29/7883 , G11C16/0425 , G11C16/0433 , H01L27/115 , H01L29/42328
摘要： A drain region and a source region are formed in a silicon substrate, and a select gate is formed on the substrate between the source and drain regions with a gate insulating film sandwiched. On one side of the select gate, a floating-gate is formed out of a sidewall formed with an insulating film sandwiched. On the floating-gate and the select gate, a control gate is formed with an insulating film sandwiched. The insulating film directly below the floating-gate is formed as a tunnel oxide film which can allow FN tunneling of electrons. In an erase operation, electrons are injected into the floating-gate from the silicon substrate, and in a write operation, electrons are extracted from the floating-gate to the drain region. A current required for writing and erasing each cell can be decreased, a low power supply can be used, and the lifetime of the tunnel insulating film can be elongated. Thus, the invention provides a semiconductor storage device (EEPROM) which works as a nonvolatile memory capable of page erase and page write at a low supply voltage.
摘要翻译：漏极区域和源极区域形成在硅衬底中，并且在栅极绝缘膜夹在源极和漏极区域之间的衬底上形成选择栅极。在选择栅极的一侧，由夹在绝缘膜上形成的侧壁形成浮栅。在浮栅和选择栅极上，形成有夹在绝缘膜上的控制栅极。直接在浮栅之下的绝缘膜形成为可以允许电子的FN隧穿的隧道氧化膜。在擦除操作中，电子从硅衬底注入到浮置栅极中，并且在写入操作中，电子从浮置栅极提取到漏极区域。可以减少写入和擦除每个单元所需的电流，可以使用低电源，并且可以延长隧道绝缘膜的寿命。因此，本发明提供一种半导体存储装置（EEPROM），其作为能够以低电源电压进行页擦除和页写入的非易失性存储器。

10. 发明授权

US06346725B1 Contact-less array of fully self-aligned, triple polysilicon, source-side injection, nonvolatile memory cells with metal-overlaid wordlines 失效
标题翻译：完全自对准，三重多晶硅，源侧注入，金属叠加字线的非易失性存储单元的非接触式阵列
公开(公告)号：US06346725B1
公开(公告)日：2002-02-12
申请号：US09083770
申请日：1998-05-22
申请人： Yueh Yale Ma , Takahiro Fukumoto
发明人： Yueh Yale Ma , Takahiro Fukumoto
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , Y10S257/90
摘要： A contact-less array of self-aligned, triple polysilicon, source side injection, nonvolatile memory cells with metal-overlaid wordlines includes: a plurality of pairs of stacks of first, second and third layer polysilicon arrange in rows; a drain region between the two stacks in each pair of polysilicon stacks, the drain regions being self-aligned to the edges of the two stacks; and a source region between each of the two adjacent pairs of polysilicon stacks, the source regions being self-aligned to side-wall spacers formed adjacent to edges of the polysilicon stacks such that each source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is located.
摘要翻译：具有金属覆盖的字线的自对准三重多晶硅，源侧注入，非易失性存储单元的无接触阵列包括：排成行的多对第一，第二和第三层多晶硅堆叠; 在每对多晶硅堆叠中的两个堆叠之间的漏极区域，漏极区域与两个堆叠的边缘自对准; 以及在两个相邻的多晶硅堆叠对中的每一个之间的源极区域，源极区域与邻近多晶硅堆叠的边缘形成的侧壁间隔物自对准，使得每个源极区域横向间隔开距离两个堆叠的多晶硅，源区域位于其间。

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