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1. 发明授权

US5838677A Switching system having means for congestion control by monitoring packets in a shared buffer and by suppressing the reading of packets from input buffers 失效
标题翻译：具有用于通过监视共享缓冲器中的分组并通过抑制从输入缓冲器读取分组的拥塞控制的交换系统
公开(公告)号：US5838677A
公开(公告)日：1998-11-17
申请号：US633306
申请日：1996-04-15
申请人： Takahiko Kozaki , Masahiro Takatori , Noboru Endo , Akihiko Takase , Yozo Oguri
发明人： Takahiko Kozaki , Masahiro Takatori , Noboru Endo , Akihiko Takase , Yozo Oguri
IPC分类号： H04Q3/545 , H04L12/70 , H04L12/801 , H04L12/911 , H04L12/931 , H04L12/937 , H04Q3/00 , H04Q11/04
CPC分类号： H04L12/5601 , H04L49/3081 , H04Q11/0478 , H04L2012/5635 , H04L2012/5647 , H04L2012/5679 , H04L2012/5681
摘要： In a switching system connected between a plurality of input lines and a plurality of output lines, destinations of a plurality of cells incoming from the plurality of input lines are monitored to detect an output line in a congestion state. Upon detection of the output line in an congestion state, congestion information indicating the output line in the congestion state is generated and added to the output cells. An input buffer control circuit derives the congestion information from the received cell, and performs buffering of a cell or cells in an input buffer, which cells are distributed to the output line in the congested state, among cells input from the input line.
摘要翻译：在连接在多个输入线和多个输出线之间的开关系统中，监视从多条输入线进入的多个单元的目的地，以检测拥塞状态下的输出线。在拥塞状态下检测到输出线路时，生成表示拥塞状态的输出线路的拥塞信息，并将其加到输出单元。输入缓冲器控制电路从接收到的单元导出拥塞信息，并且在从输入行输入的单元之间执行在输入缓冲器中的单元或单元的缓冲，哪些单元以拥塞状态分配给输出线。

2. 发明授权

US5570368A Cell multiplexer having cell delineation function 失效
标题翻译：信元复用器具有信元描绘功能
公开(公告)号：US5570368A
公开(公告)日：1996-10-29
申请号：US409691
申请日：1995-03-24
申请人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
发明人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
IPC分类号： H04J3/24 , H04L7/04 , H04L12/70 , H04Q11/04 , H04L12/56
CPC分类号： H04J3/247 , H04L7/048 , H04Q11/0478 , H04L2007/045 , H04L2012/5616 , H04L2012/5647 , H04L2012/5652 , H04L2012/5672 , H04L2012/5674
摘要： A cell multiplexer includes a multiplexing unit for time-divisionally multiplexing ATM cell signals given from a plurality of input lines, a write controller for storing cell signals outputted from the multiplexing unit in a buffer memory successively correspondingly to the input lines, a read controller for reading the cell signals stored in the buffer memory from the buffer memory in the form of data blocks synchronized with an ATM cell structure, and a cell delineation controller for detecting delineation states of the data blocks read out from the buffer memory, notifying the read controller of delineation control information corresponding to a result of the detection and transmitting data blocks read out in synchronism with a predetermined cell structure to the output line selectively, wherein the read controller determines the read beginning addresses of data blocks to be read out nextly correspondingly to the input lines on the basis of the delineation control information notified by the cell delineation controller.
摘要翻译：单元多路复用器包括用于对多个输入线提供的ATM信元进行时分多路复用的复用单元，用于将连续相应于输入线的多路复用单元输出的单元信号存储在缓冲存储器中的读控制器，以与ATM单元结构同步的数据块的形式从缓冲存储器读取存储在缓冲存储器中的单元信号;以及单元描绘控制器，用于检测从缓冲存储器读出的数据块的描画状态，通知读取控制器选择对应于与预定单元结构同步地读出的数据块的检测结果对应的描画控制信息到所述输出行，其中，所述读取控制器确定与所述读取控制信息相对应地读出的数据块的读取开始地址输入线根据描绘控制信息通知由细胞描绘控制器编辑。

3. 发明授权

US5768274A Cell multiplexer having cell delineation function 失效
公开(公告)号：US5768274A
公开(公告)日：1998-06-16
申请号：US678659
申请日：1996-07-11
申请人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
发明人： Masaru Murakami , Yozo Oguri , Yoshihiro Ashi , Katsuyoshi Tanaka , Takahiko Kozaki , Akihiko Takase , Morihito Miyagi
IPC分类号： H04J3/24 , H04L7/04 , H04L12/70 , H04Q11/04 , H04L12/56
CPC分类号： H04J3/247 , H04L7/048 , H04Q11/0478 , H04L2007/045 , H04L2012/5616 , H04L2012/5647 , H04L2012/5652 , H04L2012/5672 , H04L2012/5674
摘要： A cell multiplexer includes a multiplexing unit for time-divisionally multiplexing ATM cell signals given from a plurality of input lines, a write controller for storing cell signals outputted from the multiplexing unit in a buffer memory successively correspondingly to the input lines, a read controller for reading the cell signals stored in the buffer memory from the buffer memory in the form of data blocks synchronized with an ATM cell structure, and a cell delineation controller for detecting delineation states of the data blocks read out from the buffer memory, notifying the read controller of delineation control information corresponding to a result of the detection and transmitting data blocks read out in synchronism with a predetermined cell structure to the output line selectively, wherein the read controller determines the read beginning addresses of data blocks to be read out nextly correspondingly to the input lines on the basis of the delineation control information notified by the cell delineation controller.

4. 发明授权

US06330227B1 Cell output control apparatus and method 失效
标题翻译：单元输出控制装置及方法
公开(公告)号：US06330227B1
公开(公告)日：2001-12-11
申请号：US09382669
申请日：1999-08-25
申请人： Kota Miyoshi , Takahiko Kozaki , Hajime Abe , Akihiko Takase
发明人： Kota Miyoshi , Takahiko Kozaki , Hajime Abe , Akihiko Takase
IPC分类号： G06F1100
CPC分类号： H04L12/5602 , H04L41/00 , H04L2012/5632 , H04L2012/5635 , H04L2012/5649 , H04L2012/5658 , H04L2012/5667 , H04L2012/5679 , H04Q11/0478
摘要： The cell output control apparatus includes a cell time slot allotment circuit for allotting, cells to be transmitted, to cell time slots with the cell transmission intervals changed, a first holder circuit for holding the value of ACR (Allowed Cell Rate), a first calculator circuit for calculating the ratio, LCR (Line Cell Rate)/ACR, a quantizer circuit for quantizing the ratio, LCR/ACR and controlling the allotment of cell time slots on the basis of the quantization error produced by the quantization, a counter for counting the values of cell time slots, a second calculator circuit for calculating the cell time slots for cells, and a second holder circuit for holding the calculated results, whereby it is possible to absorb the quantization error produced when the ratio, LCR/ACR is quantized into an integral value.
摘要翻译：小区输出控制装置包括：小区时隙分配电路，用于将发送的小区分配给小区发送间隔改变的小区时隙，用于保持ACR（允许小区率）的值的第一保持电路，第一计算器用于计算比率的电路，LCR（线路单元速率）/ ACR，用于量化比率的量化器电路，LCR / ACR，并且基于由量化产生的量化误差来控制单元时隙的分配，用于计数的计数器单元时隙的值，用于计算单元的单元格时隙的第二计算器电路和用于保持所计算的结果的第二保持器电路，由此可以吸收当比率LCR / ACR被量化时产生的量化误差成为一个整体价值。

5. 发明授权

US5280475A Traffic shaping method and circuit 失效
标题翻译：流量整形方法及电路
公开(公告)号：US5280475A
公开(公告)日：1994-01-18
申请号：US745466
申请日：1991-08-14
申请人： Junichirou Yanagi , Akihiko Takase , Takahiko Kozaki , Shinobu Gohara
发明人： Junichirou Yanagi , Akihiko Takase , Takahiko Kozaki , Shinobu Gohara
IPC分类号： H04Q3/00 , H04L12/815 , H04L12/863 , H04L12/931 , H04L12/951 , H04Q11/04 , H04L12/56
CPC分类号： H04L12/5601 , H04L12/5602 , H04L49/108 , H04L49/255 , H04L49/3081 , H04Q11/0478 , H04L2012/568
摘要： A traffic shaping method and circuit of a packet switching system in which input packets having a fixed length and multiplexed on a plurality of inputs are multiplexed to be delivered on any output of a plurality of outputs, connects the input packet to a list structure using an address chain formed for each output, forms the list structure even for each line identifier provided in the packet, and assigns the identifier for each time slot of the output to take out the packet from the list structure, to thereby prevent the packet having the same identifier from being multiplexed and delivering to the output continuously.
摘要翻译：一种分组交换系统的流量整形方法和电路，其中具有固定长度并在多个输入上复用的输入分组被多路复用以在多个输出的任何输出上传送，将输入分组连接到列表结构，使用为每个输出形成的地址链，甚至对于分组中提供的每个行标识符也形成列表结构，并且分配输出的每个时隙的标识符以从列表结构中取出分组，从而防止具有相同的分组标识符被多路复用并连续传送到输出。

6. 发明授权

US5394397A Shared buffer memory type ATM communication system and method with a broadcast facility 失效
标题翻译：共享缓冲存储器类型ATM通信系统和方法与广播设施
公开(公告)号：US5394397A
公开(公告)日：1995-02-28
申请号：US38615
申请日：1993-03-29
申请人： Junichirou Yanagi , Yoshihiro Ashi , Takahiko Kozaki , Akihiko Takase , Takashi Nakashima
发明人： Junichirou Yanagi , Yoshihiro Ashi , Takahiko Kozaki , Akihiko Takase , Takashi Nakashima
IPC分类号： H04M3/42 , H04L12/18 , H04L12/761 , H04L12/931 , H04L12/951 , H04Q3/52 , H04Q11/04 , H04L12/56 , H04J3/26 , H04L12/48
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/309
摘要： An ATM switching system which includes an input interface which is provided every incoming line and serves to convert header information of each input cell into internal routing information, a shared buffer memory and a cell writing control unit which forms normal cell list structures, which are prepared in correspondence to outgoing lines and in which a plurality of normal cells are chained together with their next addresses, and a broadcast cell list structure, in which a plurality of broadcast cells are chained together with their next addresses, in the shared buffer memory, and serves to add successively the input cells to ones of the list structures, which are selected in correspondence to respective internal routing information. The invention also includes a cell reading control unit which serves to fetch selectively the cell from the list structures formed in the shared buffer memory to distribute the cell thus fetched to the associated outgoing lines. The cell reading control unit includes a broadcast destination table for "storing broadcast destination specifying information for specifying the outgoing lines, through which the broadcast cell is to be output, using a bit pattern, in correspondence to the internal routing information of the broadcast cell".
摘要翻译：一种ATM交换系统，其包括为每条输入线路提供的输入接口，用于将每个输入单元的头信息转换为内部路由信息，共享缓冲存储器和形成正常小区列表结构的小区写入控制单元，其被准备对应于输出线，并且其中多个正常小区与其下一个地址一起链接在一起，以及广播小区列表结构，其中多个广播小区与其下一个地址一起连接在共享缓冲存储器中，以及用于将输入单元连续地添加到与各个内部路由信息相对应地选择的列表结构中的一个。本发明还包括一个单元读取控制单元，用于从形成在共享缓冲存储器中的列表结构中选择性地提取单元，以将由此提取的单元分配到相关联的输出行。小区读取控制单元包括：广播目的地表，用于根据广播小区的内部路由信息，使用位模式存储用于指定要输出广播小区的出行的广播目的地指定信息; 。

7. 发明授权

US6021128A Asynchronous transfer mode switching system 失效
标题翻译：异步传输模式切换系统
公开(公告)号：US6021128A
公开(公告)日：2000-02-01
申请号：US814649
申请日：1997-03-10
申请人： Mutsumi Hosoya , Morihito Miyagi , Willy Hioe , Akihiko Takase , Takahiko Kozaki , Toshikazu Nishino
发明人： Mutsumi Hosoya , Morihito Miyagi , Willy Hioe , Akihiko Takase , Takahiko Kozaki , Toshikazu Nishino
IPC分类号： H04Q3/00 , H04L12/70 , H04L12/931 , H04L12/933 , H04Q3/52 , H04Q11/04 , H04L12/50 , H04L12/56 , H04Q11/00
CPC分类号： H04Q11/0478 , H04L2012/5649
摘要： An asynchronous transfer mode switching system for improving switching throughput and averting complicated and difficult timing design. In operation, synchronous cell strings from external transmission lines are converted to asynchronous cell strings which are switched by a space-division switch array. The switched asynchronous cell strings are reconverted to synchronous cell strings for output onto external transmission lines. The space-division switch array comprises a plurality of unit switches in stages, each unit switch having input terminals and output terminals. The unit switches each include a timing control circuit that causes a switching operation to start upon detecting two states concurrently: a stored state of a cell to be switched, and a storage-ready state of a destination for the switched cell. The scheme allows the system to operate in an asynchronous manner.
摘要翻译：一种异步传输模式切换系统，用于提高交换吞吐量并避免复杂而困难的时序设计。在操作中，来自外部传输线的同步单元串被转换成由空分开关阵列切换的异步单元串。交换的异步单元串被重新转换为同步单元串，以输出到外部传输线。空分开关阵列分为多个单元开关，每个单元开关具有输入端子和输出端子。单元开关每个包括定时控制电路，其在同时检测两个状态时使开关操作开始：待切换的单元的存储状态和用于切换的单元的目的地的存储就绪状态。该方案允许系统以异步方式运行。

8. 发明授权

US6002668A Cell output control apparatus and method 失效
标题翻译：单元输出控制装置及方法
公开(公告)号：US6002668A
公开(公告)日：1999-12-14
申请号：US810733
申请日：1997-03-04
申请人： Kota Miyoshi , Takahiko Kozaki , Hajime Abe , Akihiko Takase
发明人： Kota Miyoshi , Takahiko Kozaki , Hajime Abe , Akihiko Takase
IPC分类号： H04Q3/00 , H04L12/24 , H04L12/801 , H04L12/811 , H04L12/911 , H04Q11/04 , G06F11/00 , H04L12/56 , H04L3/22
CPC分类号： H04L12/5602 , H04L12/24 , H04L41/00 , H04Q11/0478 , H04L2012/5632 , H04L2012/5635 , H04L2012/5649 , H04L2012/5658 , H04L2012/5667 , H04L2012/5679
摘要： The cell output control apparatus includes a cell time slot allotment circuit for allotting, cells to be transmitted, to cell time slots with the cell transmission intervals changed, a first holder circuit for holding the value of ACR (Allowed Cell Rate), a first calculator circuit for calculating the ratio, LCR (Line Cell Rate)/ACR, a quantizer circuit for quantizing the ratio, LCR/ACR and controlling the allotment of cell time slots on the basis of the quantization error produced by the quantization, a counter for counting the values of cell time slots, a second calculator circuit for calculating the cell time slots for cells, and a second holder circuit for holding the calculated results, whereby it is possible to absorb the quantization error produced when the ratio, LCR/ACR is quantized into an integral value.
摘要翻译：小区输出控制装置包括：小区时隙分配电路，用于将发送的小区分配给小区发送间隔改变的小区时隙，用于保持ACR（允许小区率）的值的第一保持电路，第一计算器用于计算比率的电路，LCR（线路单元速率）/ ACR，用于量化比率的量化器电路，LCR / ACR，并且基于由量化产生的量化误差来控制单元时隙的分配，用于计数的计数器单元时隙的值，用于计算单元的单元格时隙的第二计算器电路和用于保持所计算的结果的第二保持器电路，由此可以吸收当比率LCR / ACR被量化时产生的量化误差成为一个整体价值。

9. 发明授权

US6046999A Router apparatus using ATM switch 失效
公开(公告)号：US6046999A
公开(公告)日：2000-04-04
申请号：US28830
申请日：1998-02-13
申请人： Kazuho Miki , Masahiro Takatori , Akihiko Takase , Masaru Murakami , Koji Wakayama , Tetsuro Yoshimoto , Masao Kunimoto
发明人： Kazuho Miki , Masahiro Takatori , Akihiko Takase , Masaru Murakami , Koji Wakayama , Tetsuro Yoshimoto , Masao Kunimoto
IPC分类号： H04J3/04 , H04L12/28 , H04L12/56 , H04L12/66
CPC分类号： H04L49/25 , H04L12/5601 , H04L49/3072 , H04L49/602 , H04L49/606 , H04L2012/5667 , H04L2012/567
摘要： A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.

10. 发明授权

US5042027A Communication network system and method of controlling a communication network 失效
标题翻译：通信网络系统和控制通信网络的方法
公开(公告)号：US5042027A
公开(公告)日：1991-08-20
申请号：US404535
申请日：1989-09-08
申请人： Akihiko Takase , Masahiro Takatori , Yoshiaki Takemura , Naoya Kobayashi , Yasushi Sawada , Yukio Nakano , Yasushi Takahashi , Masahiro Koya , Yoshitaka Takasaki
发明人： Akihiko Takase , Masahiro Takatori , Yoshiaki Takemura , Naoya Kobayashi , Yasushi Sawada , Yukio Nakano , Yasushi Takahashi , Masahiro Koya , Yoshitaka Takasaki
IPC分类号： H04M3/36 , H04L12/24 , H04L12/801 , H04L12/911 , H04M3/00 , H04Q3/66
CPC分类号： H04L45/00 , H04Q3/66 , H04Q2213/13141 , H04Q2213/13164 , H04Q2213/13166 , H04Q2213/13332 , H04Q2213/13353
摘要： A communication network system includes a communication line, a plurality of communication stations each having a node coupled to the communication line and a network controller coupled to the stations for controlling routing for communication messages between nodes. In one embodiment, the messages are sent from plural terminals connected with each node along with communication performance prerequisites. The communication performance prerequisites for a communication message are discriminated in the node which receives the message. Traffic in various routes between the nodes is continually measured in the communication stations and the measuring results are stored in a database storage unit. Future traffic in the various routes is predicted on the basis of the information on the continually measured traffic by the use of a predetermined algorithm and stored in the storage unit for use in determination of routes for communication messages on the basis of the result of the communication performance prerequisites discrimination and predetermined criteria with respect to the updated information on the predicted traffic in the storage unit.
摘要翻译：通信网络系统包括通信线路，多个通信站，每个通信站具有耦合到通信线路的节点，以及耦合到该站点的网络控制器，用于控制节点之间的通信消息的路由。在一个实施例中，从与每个节点连接的多个终端以及通信性能先决条件发送消息。通信消息的通信性能先决条件在接收消息的节点中被区分。在通信站中连续测量节点之间的各种路由的流量，并将测量结果存储在数据库存储单元中。基于通过使用预定算法的连续测量的业务的信息来预测各种路线中的未来业务，并且存储在存储单元中以用于基于通信的结果确定通信消息的路由性能先决条件判定和关于存储单元中预测业务量的更新信息的预定标准。

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