专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07439577B2 Semiconductor memory and method for manufacturing the same 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US07439577B2
公开(公告)日：2008-10-21
申请号：US11495780
申请日：2006-07-31
申请人： Takahiko Hashidzume , Nobuyoshi Takahashi , Koji Yoshida , Keita Takahashi , Kiyoshi Kurihara , Yoshiya Moriyama
发明人： Takahiko Hashidzume , Nobuyoshi Takahashi , Koji Yoshida , Keita Takahashi , Kiyoshi Kurihara , Yoshiya Moriyama
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.
摘要翻译：半导体存储器设置有存储单元，存储单元包括由在半导体衬底中形成的扩散层构成的位线，形成在位线和形成在栅极绝缘膜上的字线之间的电荷俘获栅极绝缘膜。在存储单元之上形成层间绝缘膜，并且在层间绝缘膜中形成位线接触插塞以连接到位线。此外，在覆盖存储单元的层间绝缘膜的至少一部分上形成遮光膜，并且形成在层间绝缘膜上的遮光膜的一部分从层间绝缘膜的表面延伸到附近的层间绝缘膜的内部位线接触插头。

2. 发明申请

US20070108509A1 Semiconductor memory and method for manufacturing the same 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20070108509A1
公开(公告)日：2007-05-17
申请号：US11495780
申请日：2006-07-31
申请人： Takahiko Hashidzume , Nobuyoshi Takahashi , Koji Yoshida , Keita Takahashi , Kiyoshi Kurihara , Yoshiya Moriyama
发明人： Takahiko Hashidzume , Nobuyoshi Takahashi , Koji Yoshida , Keita Takahashi , Kiyoshi Kurihara , Yoshiya Moriyama
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.
摘要翻译：半导体存储器设置有存储单元，存储单元包括由在半导体衬底中形成的扩散层构成的位线，形成在位线和形成在栅极绝缘膜上的字线之间的电荷俘获栅极绝缘膜。在存储单元之上形成层间绝缘膜，并且在层间绝缘膜中形成位线接触插塞以连接到位线。此外，在覆盖存储单元的层间绝缘膜的至少一部分上形成遮光膜，并且形成在层间绝缘膜上的遮光膜的一部分从层间绝缘膜的表面延伸到附近的层间绝缘膜的内部位线接触插头。

3. 发明授权

US07446381B2 Semiconductor memory device and method for fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07446381B2
公开(公告)日：2008-11-04
申请号：US11151542
申请日：2005-06-14
申请人： Takahiko Hashidzume , Fumihiko Noro , Nobuyoshi Takahashi
发明人： Takahiko Hashidzume , Fumihiko Noro , Nobuyoshi Takahashi
IPC分类号： H01L29/72
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11568
摘要： A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.
摘要翻译：半导体存储器件具有形成在半导体衬底上的存储区域，其中使用多个杂质扩散层（位线）和多个栅极电极将包括存储晶体管的多个存储单元布置为矩阵（字线）相交。每个存储晶体管的栅极电极的上表面形成为在中间部分高于边缘部分的高度的突出部分。在每个存储晶体管的栅电极的突出部分的上表面上形成硅化物层。

4. 发明申请

US20060022243A1 Semiconductor memory device and method for fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20060022243A1
公开(公告)日：2006-02-02
申请号：US11151542
申请日：2005-06-14
申请人： Takahiko Hashidzume , Fumihiko Noro , Nobuyoshi Takahashi
发明人： Takahiko Hashidzume , Fumihiko Noro , Nobuyoshi Takahashi
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11568
摘要： A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.
摘要翻译：半导体存储器件具有形成在半导体衬底上的存储区域，其中使用多个杂质扩散层（位线）和多个栅电极将包括存储晶体管的多个存储单元布置为矩阵（字线）相交。每个存储晶体管的栅极电极的上表面形成为在中间部分高于边缘部分的高度的突出部分。在每个存储晶体管的栅电极的突出部分的上表面上形成硅化物层。

5. 发明授权

US06872624B2 Method of fabricating nonvolatile semiconductor memory device 失效
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US06872624B2
公开(公告)日：2005-03-29
申请号：US09987001
申请日：2001-11-13
申请人： Yoshinori Odake , Fumihiko Noro , Takahiko Hashidzume
发明人： Yoshinori Odake , Fumihiko Noro , Takahiko Hashidzume
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A gate structure composed of a tunnel insulation film, a floating gate electrode, a capacitive insulation film and a control gate electrode is formed on a semiconductor substrate. Then, ion injection adjustment films that are in contact with the floating gate electrode at least on the side surfaces of the floating gate electrode are formed. After injecting impurity ions into the active region beside the gate structure in the semiconductor substrate while using the gate structure and the ion injection adjustment film as masks, the injected impurity ions are diffused thermally by performing heat treatment on the active region. Film thickness of the ion injection adjustment film is selected to a value to prevent the impurity ions from being injected into the tunnel insulation film and allows the impurity ions to reach lower portions of side end of the floating gate electrode in the active region as a result of diffusive scattering of impurity ions in the semiconductor substrate.
摘要翻译：在半导体衬底上形成由隧道绝缘膜，浮栅电极，电容绝缘膜和控制栅电极构成的栅极结构。然后，形成至少在浮栅电极的侧面与浮栅电极接触的离子注入调节膜。在使用栅极结构和离子注入调节膜作为掩模的同时，在半导体衬底中的栅极结构旁边的有源区域中注入杂质离子之后，通过对活性区域进行热处理，注入的杂质离子被热扩散。选择离子注入调节膜的膜厚为防止杂质离子注入到隧道绝缘膜中的值，从而允许杂质离子到达活性区域中的浮栅电极的侧端的下部，结果在半导体衬底中杂质离子的漫射散射。

6. 发明授权

US06597047B2 Method for fabricating a nonvolatile semiconductor device 失效
标题翻译：非易失性半导体器件的制造方法
公开(公告)号：US06597047B2
公开(公告)日：2003-07-22
申请号：US09813305
申请日：2001-03-21
申请人： Masatoshi Arai , Takahiko Hashidzume
发明人： Masatoshi Arai , Takahiko Hashidzume
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A silicon dioxide film, located over an active region in a well, is annealed at 1050° C. within an N2O ambient, thereby diffusing nitrogen into the silicon dioxide film and forming a nitrogen-containing silicon dioxide film. Next, two polysilicon films, interposing an ONO film therebetween, are deposited and then those films are patterned. In this manner, a memory gate electrode section, consisting of floating gate electrode, interelectrode insulating film and control gate electrode, is formed on the nitrogen-containing silicon dioxide film as a tunnel insulating film. At the same time, a select gate electrode section is also formed beside the memory gate electrode section. Then, p-type source/drain regions and intermediate diffused region are defined below these electrode sections. In this structure, electrons can be injected through a particular part of the tunnel insulating film and holes are trapped in a limited region of the tunnel insulating film.
摘要翻译：位于阱中的有源区上的二氧化硅膜在N2O环境中在1050℃退火，从而将氮扩散到二氧化硅膜中并形成含氮二氧化硅膜。接下来，沉积两个多晶硅膜，在其间插入ONO膜，然后将这些膜图案化。以这种方式，在作为隧道绝缘膜的含氮二氧化硅膜上形成由浮栅电极，电极间绝缘膜和控制栅电极构成的存储栅电极部。同时，在存储栅电极部分旁边也形成选择栅电极部分。然后，在这些电极部分下方限定p型源极/漏极区域和中间扩散区域。在这种结构中，可以通过隧道绝缘膜的特定部分注入电子，并且孔被捕获在隧道绝缘膜的有限区域中。

7. 发明授权

US06538937B2 Nonvolatile semiconductor memory test circuit and method, nonvolatile semiconductor memory and method for fabricating nonvolatile semiconductor memory 有权
公开(公告)号：US06538937B2
公开(公告)日：2003-03-25
申请号：US09930968
申请日：2001-08-17
申请人： Takahiko Hashidzume , Yoshinori Odake
发明人： Takahiko Hashidzume , Yoshinori Odake
IPC分类号： G11C700
CPC分类号： G11C29/50 , H01L21/28273 , H01L27/11521
摘要： A circuit for testing a nonvolatile semiconductor memory includes a serial connection of flash memory cells as a first memory group. In the serial connection, the gates of the flash memory cells have been connected to each other, and a first one of the cells has its source or drain connected to the source or drain of a second one of the cells when the first and second cells are adjacent to each other.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式