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1. 发明授权

US5354699A Method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5354699A
公开(公告)日：1994-10-11
申请号：US964824
申请日：1992-10-22
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

2. 发明授权

US5512497A Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US5512497A
公开(公告)日：1996-04-30
申请号：US272312
申请日：1994-07-08
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265 , H01L21/8238
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

3. 发明授权

US5057894A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5057894A
公开(公告)日：1991-10-15
申请号：US526696
申请日：1990-05-23
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/285 , H01L21/8249 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/28525 , H01L21/8249
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

4. 发明授权

US4984200A Semiconductor circuit device having a plurality of SRAM type memory cell arrangement 失效
标题翻译：具有多个SRAM型存储单元布置的半导体电路装置
公开(公告)号：US4984200A
公开(公告)日：1991-01-08
申请号：US271309
申请日：1988-11-15
申请人： Ryuichi Saitoo , Osamu Saitoo , Takahide Ikeda , Mitsuru Hirao , Atsushi Hiraishi
发明人： Ryuichi Saitoo , Osamu Saitoo , Takahide Ikeda , Mitsuru Hirao , Atsushi Hiraishi
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： G11C11/412 , H01L27/1112 , Y10S257/904 , Y10S257/906
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM which is composed of a memory cell having its high resistance load element and power source voltage line connected with the information storage node of a flip-flop circuit through a conductive layer. At the same fabrication step as that of forming the plate electrode layer of a capacity element over the conductive layer formed on the portion of the information storage node through a dielectric film, an electric field shielding film for shielding the field effect of a data line is formed over the high resistance load element through an inter-layer insulation film.
摘要翻译：这里公开了一种包括SRAM的半导体集成电路器件，SRAM由具有高电阻负载元件的存储单元和通过导电层与触发器电路的信息存储节点连接的电源电压线组成。在与通过电介质膜形成在信息存储节的部分上的导电层上形成电容元件的平板电极层相同的制造步骤中，用于屏蔽数据线的场效应的电场屏蔽膜是通过层间绝缘膜形成在高电阻负载元件上。

5. 发明授权

US4963973A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4963973A
公开(公告)日：1990-10-16
申请号：US323212
申请日：1989-03-13
申请人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
发明人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0623 , H01L21/8238 , H01L21/8249 , Y10S257/921
摘要： A semiconductor device has a well region formed in the surface of a substrate, and has semiconductor elements such as MOSFETs and bipolar transistors formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
摘要翻译：半导体器件具有在衬底的表面中形成的阱区，并且在阱区中形成有诸如MOSFET和双极晶体管的半导体元件。阱区域的载流子浓度分布呈深谷方向的谷状，其最小点浓度小于5×10 15 cm -3，位于距离其表面1.6m以内的位置底物。优选地，最小点应该具有大于5×10 14 cm -3但小于5×10 15 cm -3的浓度，更优选大于1×10 15 cm -3但小于5×10 15 cm -3的浓度。

6. 发明授权

US5726488A Semiconductor device having semiconductor elements formed in a retrograde well structure 失效
标题翻译：具有形成在逆行井结构中的半导体元件的半导体器件
公开(公告)号：US5726488A
公开(公告)日：1998-03-10
申请号：US243325
申请日：1994-05-16
申请人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
发明人： Atsuo Watanabe , Yoshiaki Yazawa , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano , Takahide Ikeda , Naohiro Momma
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78 , H01L27/02
CPC分类号： H01L27/0623 , H01L21/8238 , H01L21/8249 , Y10S257/921
摘要： A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
摘要翻译：半导体器件具有在衬底的表面中形成的阱区，并且具有形成在阱区中的诸如MOSFET和双极晶体管的功能部分。阱区域的载流子浓度分布呈深谷方向的谷状，其最小点浓度小于5×10 15 cm -3，位于距离其表面1.6m以内的位置底物。优选地，最小点应该具有大于5×10 14 cm -3但小于5×10 15 cm -3的浓度，更优选大于1×10 15 cm -3但小于5×10 15 cm -3的浓度。

7. 发明授权

US4916500A MOS field effect transistor device with buried channel 失效
标题翻译： MOS场效应晶体管器件具有埋入通道
公开(公告)号：US4916500A
公开(公告)日：1990-04-10
申请号：US78987
申请日：1987-07-29
申请人： Yoshiaki Yazawa , Atsuo Watanabe , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano
发明人： Yoshiaki Yazawa , Atsuo Watanabe , Atsushi Hiraishi , Masataka Minami , Takahiro Nagano
IPC分类号： H01L29/10 , H01L29/78 , H01L29/786 , H01L29/808
CPC分类号： H01L29/78696 , H01L29/105 , H01L29/78 , H01L29/7838 , H01L29/808
摘要： The present invention relates to a semiconductor device comprising a semiconductor substrate of a first conductivity type or an insulator, a source comprising an impurity layer of a second conductivity type disposed on said semiconductor substrate or said insulator, a drain comprising an impurity layer of the second conductivity type disposed on said semiconductor substrate or said insulator, an impurity layer of the first conductivity type formed between said source and said drain, a gate formed on said impurity layer of the first conductivity type via an insulation film, and an impurity layer of the second conductivity type having an impurity concentration lower than that of said source and said drain, said impurity layer of the second conductivity type being disposed between said source, said drain and said impurity layer of the first conductivity type, and said semiconductor substrate of the first conductivity type or said insulator.
摘要翻译：本发明涉及一种包括第一导电类型或绝缘体的半导体衬底的半导体器件，包括设置在所述半导体衬底或所述绝缘体上的第二导电类型的杂质层的源极，包括第二导电类型或绝缘体的杂质层的漏极设置在所述半导体衬底或所述绝缘体上的导电类型，形成在所述源极和所述漏极之间的第一导电类型的杂质层，经由绝缘膜形成在所述第一导电类型的所述杂质层上的栅极和第二导电类型的杂质浓度低于所述源极和漏极的第二导电类型，所述第二导电类型的所述杂质层设置在所述源极，所述漏极和所述第一导电类型的所述杂质层之间，所述第一导电类型的所述半导体衬底导电类型或所述绝缘体。

8. 发明授权

US08922029B2 Apparatus having a wiring board and memory devices 有权
标题翻译：具有接线板和存储器件的设备
公开(公告)号：US08922029B2
公开(公告)日：2014-12-30
申请号：US13363396
申请日：2012-02-01
申请人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
发明人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , G11C5/06 , G11C5/04 , G11C8/14 , H05K1/18
CPC分类号： G11C5/063 , G11C5/04 , G11C8/14 , H05K1/181 , H05K2201/09254 , H05K2201/09263 , H05K2201/10159 , Y02P70/611
摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
摘要翻译：具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

9. 发明申请

US20100309706A1 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US20100309706A1
公开(公告)日：2010-12-09
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

10. 发明授权

US07667317B2 Semiconductor package with bypass capacitor 失效
标题翻译：带旁路电容器的半导体封装
公开(公告)号：US07667317B2
公开(公告)日：2010-02-23
申请号：US11802888
申请日：2007-05-25
申请人： Fumiyuki Osanai , Atsushi Hiraishi , Toshio Sugano , Tsuyoshi Tomoyama , Satoshi Isa , Masahiro Yamaguchi , Masanori Shibamoto
发明人： Fumiyuki Osanai , Atsushi Hiraishi , Toshio Sugano , Tsuyoshi Tomoyama , Satoshi Isa , Masahiro Yamaguchi , Masanori Shibamoto
IPC分类号： H01L23/055
CPC分类号： H01L23/50 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/19041 , H01L2924/3011 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.
摘要翻译：半导体封装包括具有两个表面并且包括第一和第二电路径的衬底。在其中一个表面上安装了半导体芯片。半导体芯片包括多个焊盘，其包括要供应电源的第一焊盘和要接地的第二焊盘。在另一个表面上，安装至少一个旁路电容器。旁路电容器包括分别通过第一和第二电路连接到第一和第二焊盘的第一和第二端子。

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