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1. 发明申请

US20050148138A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20050148138A1
公开(公告)日：2005-07-07
申请号：US10961767
申请日：2004-10-07
申请人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
发明人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
IPC分类号： H01L21/283 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8246 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/76202 , H01L21/76224 , H01L21/823418 , H01L21/823462 , H01L27/115
摘要： A method of manufacturing a semiconductor device that has a high-breakdown-voltage transistor, a low-voltage driving transistor and a MONOS type memory transistor includes a step of forming a stack film that includes at least an oxide silicon layer and a nitride silicon layer over a high-breakdown-voltage transistor forming region where the high-breakdown-voltage transistor is formed, a low-voltage driving transistor forming region where the low-voltage driving transistor is formed and a MONOS type memory transistor forming region where the MONOS type memory transistor is formed in a semiconductor layer, a step of removing the stack film formed in a first gate insulating layer forming region of the high-breakdown-voltage transistor and a step of forming a first gate insulating layer in the high-breakdown-voltage transistor forming region by thermal oxidation. The method also includes a step of removing the stack film formed in the low-voltage driving transistor forming region, a step of forming a second gate insulating layer in the low-voltage driving transistor forming region, a step of forming gate electrodes in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MONOS type memory transistor forming region and a step of forming source/drain regions in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MONOS type memory transistor forming region.
摘要翻译：制造具有高击穿电压晶体管，低电压驱动晶体管和MONOS型存储晶体管的半导体器件的方法包括形成至少包含氧化硅层和氮化硅层的堆叠膜的步骤通过形成高击穿电压晶体管的高击穿电压晶体管形成区域，形成低电压驱动晶体管的低电压驱动晶体管形成区域和MONOS型存储晶体管形成区域存储晶体管形成在半导体层中，去除形成在高击穿电压晶体管的第一栅极绝缘层形成区域中的堆叠膜的步骤和形成高击穿电压的第一栅极绝缘层的步骤晶体管形成区域通过热氧化。该方法还包括去除在低电压驱动晶体管形成区域中形成的叠层膜的步骤，在低电压驱动晶体管形成区域中形成第二栅极绝缘层的步骤，在高电压驱动晶体管形成区域中形成栅电极的步骤低电压驱动晶体管形成区域和MONOS型存储晶体管形成区域，以及在高击穿电压晶体管形成区域中形成源极/漏极区域的步骤，低电压驱动晶体管形成区域形成区域和MONOS型存储晶体管形成区域。

2. 发明授权

US07008850B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07008850B2
公开(公告)日：2006-03-07
申请号：US10962111
申请日：2004-10-07
申请人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
发明人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/823857 , H01L21/76202 , H01L21/76224 , H01L21/823814
摘要： A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.
摘要翻译：制造其半导体器件的方法包括在同一半导体层中，其晶体管和MNOS型存储晶体管具有不同的栅极耐受电压和漏极耐受电压。

3. 发明申请

US20050130365A1 Method of manufacturing semi conductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050130365A1
公开(公告)日：2005-06-16
申请号：US10961768
申请日：2004-10-07
申请人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
发明人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
IPC分类号： H01L21/283 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L27/105 , H01L27/11546
摘要： A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.
摘要翻译：一种半导体器件的制造方法，其在同一半导体层上具有不同的高压栅极的晶体管以及高电压漏极和MNOS存储晶体管。

4. 发明授权

US07001812B2 Method of manufacturing semi conductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07001812B2
公开(公告)日：2006-02-21
申请号：US10961768
申请日：2004-10-07
申请人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
发明人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
IPC分类号： H01L21/8234
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L27/105 , H01L27/11546
摘要： A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.
摘要翻译：一种半导体器件的制造方法，其在同一半导体层上具有不同的高压栅极的晶体管以及高电压漏极和MNOS存储晶体管。

5. 发明申请

US20050118759A1 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20050118759A1
公开(公告)日：2005-06-02
申请号：US10962111
申请日：2004-10-07
申请人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
发明人： Takafumi Noda , Susumu Inoue , Masahiko Tsuyuki , Akihiko Ebina
IPC分类号： H01L21/283 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/76202 , H01L21/76224 , H01L21/823814
摘要： A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.
摘要翻译：制造其半导体器件的方法包括在同一半导体层中，其晶体管和MNOS型存储晶体管具有不同的栅极耐受电压和漏极耐受电压。

6. 发明授权

US07592684B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07592684B2
公开(公告)日：2009-09-22
申请号：US11461165
申请日：2006-07-31
申请人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
发明人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
IPC分类号： H01L27/12
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
摘要翻译：提供了一种半导体器件，其中在相同的衬底上形成有高的击穿电压晶体管和低电压驱动晶体管。所述器件包括半导体层，用于限定半导体层中的高击穿电压晶体管形成区域的第一元件隔离区域，包括用于限定半导体层中的低电压驱动晶体管形成区域的沟槽电介质层的第二元件隔离区域，高击穿电压形成在高击穿电压晶体管形成区域中的晶体管，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻形成在高击穿电压晶体管形成区域中的高击穿电压晶体管的电场的偏移电介质层，其中偏移电介质层的上端为喙状。

7. 发明申请

US20050045983A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050045983A1
公开(公告)日：2005-03-03
申请号：US10899298
申请日：2004-07-26
申请人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
发明人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/00
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823462
摘要： A semiconductor device is provided that includes a semiconductor layer, first element isolation regions defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating an electric field of the high breakdown voltage transistors, wherein the high breakdown voltage transistors have gate dielectric layers formed by a CVD method.
摘要翻译：提供一种半导体器件，其包括半导体层，在半导体层中限定高击穿电压晶体管形成区域的第一元件隔离区域，限定半导体层中的低电压驱动晶体管形成区域的第二元件隔离区域，形成的高击穿电压晶体管在高击穿电压晶体管形成区域中，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻高击穿电压晶体管的电场的偏移电介质层，其中高击穿电压晶体管形成栅极电介质层通过CVD法。

8. 发明授权

US07141862B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US07141862B2
公开(公告)日：2006-11-28
申请号：US10890403
申请日：2004-07-13
申请人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
发明人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
IPC分类号： H01L29/00
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

9. 发明申请

US20050029616A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050029616A1
公开(公告)日：2005-02-10
申请号：US10890403
申请日：2004-07-13
申请人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
发明人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/78 , H01L21/336 , H01L29/00
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
摘要翻译：提供了一种半导体器件，其中在相同的衬底上形成有高的击穿电压晶体管和低电压驱动晶体管。所述器件包括半导体层，用于限定半导体层中的高击穿电压晶体管形成区域的第一元件隔离区域，包括用于限定半导体层中的低电压驱动晶体管形成区域的沟槽电介质层的第二元件隔离区域，高击穿电压形成在高击穿电压晶体管形成区域中的晶体管，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻形成在高击穿电压晶体管形成区域中的高击穿电压晶体管的电场的偏移电介质层，其中偏移电介质层的上端为喙状。

10. 发明授权

US07163855B2 Method for manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07163855B2
公开(公告)日：2007-01-16
申请号：US10902699
申请日：2004-07-29
申请人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
发明人： Takafumi Noda , Masahiro Hayashi , Akihiko Ebina , Masahiko Tsuyuki
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823892 , H01L21/823814 , H01L21/823857 , H01L27/0922 , H01L27/0928
摘要： A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving transistor forming region.
摘要翻译：提供一种半导体器件制造方法，包括：在半导体层中形成在高击穿电压晶体管形成区域中成为第一阱的第一杂质层; 形成成为所述高击穿电压晶体管形成区域的偏移区域的第二杂质层; 通过热处理所述半导体层来扩散所述第一和第二杂质层的杂质来形成所述第一阱和所述偏移区域; 在形成第一阱和偏移区之后，通过沟槽元件隔离方法在半导体层中形成元件隔离区; 在高击穿电压晶体管形成区域中形成第一栅极电介质层; 在半导体层中的低电压驱动晶体管形成区域中形成第二阱; 在所述低电压驱动晶体管形成区域中形成第二栅极电介质层; 以及在高击穿电压晶体管形成区域和低电压驱动晶体管形成区域中形成栅电极。

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