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1. 发明授权

US06757209B2 Memory cell structural test 失效
标题翻译：记忆体结构测试
公开(公告)号：US06757209B2
公开(公告)日：2004-06-29
申请号：US09823642
申请日：2001-03-30
申请人： Tak M. Mak , Michael R. Spica , Michael J. Tripp
发明人： Tak M. Mak , Michael R. Spica , Michael J. Tripp
IPC分类号： G11C800
CPC分类号： G11C29/028 , G11C29/02 , G11C29/50 , G11C2029/5004
摘要： An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.
摘要翻译：一种用于测试存储器单元的装置和方法，包括分别将第一和第二存储器单元耦合到第一和第二位线，通过第一和第二位线从第一和第二存储器单元读取数据，以及将电压电平的第一和第二位线。

2. 发明授权

US06721216B2 Memory addressing structural test 有权
标题翻译：存储器寻址结构测试
公开(公告)号：US06721216B2
公开(公告)日：2004-04-13
申请号：US09823597
申请日：2001-03-30
申请人： Tak M. Mak , Michael R. Spica , Michael J. Tripp
发明人： Tak M. Mak , Michael R. Spica , Michael J. Tripp
IPC分类号： G11C2900
CPC分类号： G11C29/02
摘要： An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.
摘要翻译：一种用于测试存储器阵列的地址解码器和字线的装置和方法，包括将签名分析器连接到从地址解码器发出的字线，设置用于触发字线的状态的锁存的时钟通过签名分析器，将地址发送到要解码的地址解码器，并且触发签名分析器来锁定字线的状态。

3. 发明授权

US06885209B2 Device testing 有权
标题翻译：设备测试
公开(公告)号：US06885209B2
公开(公告)日：2005-04-26
申请号：US10224492
申请日：2002-08-21
申请人： Tak M. Mak , Michael J. Tripp
发明人： Tak M. Mak , Michael J. Tripp
IPC分类号： G01R29/26 , H04L1/24 , G01R31/02 , H04B3/46 , H04B17/00 , H04Q1/20
CPC分类号： H04L1/243 , G01R29/26
摘要： A testing mode is provided for self testing of the transmitter and receiver pair provided on-chip. The testing mode targets each module individually; wherein when one of the two devices is placed under test, the other is used as a tester. When the transmitter is the device under test and the receiver is the tester that receives a transmitted signal from the transmitter, the receiver is used to determine the data eye size with the transmitted signal. When the receiver is the device under test and the transmitter is the tester, the transmitter is used to determine the amount of noise and power loss tolerated by the receiver.
摘要翻译：为片上提供的发送器和接收器对的自检提供测试模式。测试模式分别针对每个模块; 其中当两个装置中的一个被放置在被测试时，另一个被用作测试器。当发射机是被测设备时，接收机是从发射机接收发射信号的测试仪，接收机用于利用发射信号确定数据眼睛尺寸。当接收机是被测设备，发射机是测试仪时，发射机用于确定接收机所容忍的噪声和功率损耗。

4. 发明授权

US07278076B2 System and scanout circuits with error resilience circuit 失效
标题翻译：具有错误恢复电路的系统和扫描电路
公开(公告)号：US07278076B2
公开(公告)日：2007-10-02
申请号：US11050996
申请日：2005-02-04
申请人： Ming Zhang , Subhasish Mitra , Tak M. Mak , Victor Zia
发明人： Ming Zhang , Subhasish Mitra , Tak M. Mak , Victor Zia
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318566 , G01R31/31816 , G01R31/318541 , G01R31/318572 , G11C2029/3202
摘要： In one embodiment, an apparatus is provided with a system circuit, a scanout circuit and an error detecting circuit. The system circuit is adapted to generate a first output signal in response to a data input signal and a system clock signal. The scanout circuit is adapted to generate a second output signal in response the data input signal and the system clock signal. The error detecting circuit, coupled to the system circuit and the scanout circuit, is adapted to generate an error signal in response to a relative condition between the first output signal and the second output signal.
摘要翻译：在一个实施例中，设备具有系统电路，扫描输出电路和错误检测电路。系统电路适于响应于数据输入信号和系统时钟信号产生第一输出信号。扫描输出电路适于响应于数据输入信号和系统时钟信号产生第二输出信号。耦合到系统电路和扫描输出电路的误差检测电路适于响应于第一输出信号和第二输出信号之间的相对条件产生误差信号。

5. 发明申请

US20140189457A1 INPUT/OUTPUT DELAY TESTING FOR DEVICES UTILIZING ON-CHIP DELAY GENERATION 有权
标题翻译：使用片上延迟生成的设备的输入/输出延迟测试
公开(公告)号：US20140189457A1
公开(公告)日：2014-07-03
申请号：US13728741
申请日：2012-12-27
申请人： Tak M. Mak , Christopher J. Nelson , David J. Zimmerman , Derek B. Feltham
发明人： Tak M. Mak , Christopher J. Nelson , David J. Zimmerman , Derek B. Feltham
IPC分类号： G01R31/3177
CPC分类号： G01R31/31716 , G01R31/3016
摘要： I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.
摘要翻译：利用片上延迟生成的器件进行I / O延迟测试。装置的实施例包括I / O缓冲电路，缓冲电路中的至少一个包括被耦合用于缓冲电路的环回测试的发射机和接收机; 以及用于所述至少一个缓冲电路的环回测试的测试电路，所述环回测试包括确定由所述缓冲器电路的发射机发送的测试数据是否与由所述相应耦合的接收机接收的测试数据相匹配。测试电路包括延迟线，用于从用于测试至少一个缓冲电路的发射时钟信号提供延迟值，提供计数以选择多个延迟值中的一个的计数器，回测试。

6. 发明授权

US07373572B2 System pulse latch and shadow pulse latch coupled to output joining circuit 有权
标题翻译：系统脉冲锁存和阴影脉冲锁存器耦合到输出接合电路
公开(公告)号：US07373572B2
公开(公告)日：2008-05-13
申请号：US11128692
申请日：2005-05-12
申请人： Tak M. Mak , Ming Zhang , Subhasish Mitra , Paul E. Shipley
发明人： Tak M. Mak , Ming Zhang , Subhasish Mitra , Paul E. Shipley
IPC分类号： G01R31/28
CPC分类号： H03K3/356156 , G01R31/318583 , H03K3/0375
摘要： In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal; and an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal.
摘要翻译：在一个实施例中，一种装置包括系统脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个系统锁存信号; 阴影脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个阴影锁存信号; 以及耦合到系统脉冲锁存器和阴影脉冲锁存器的输出连接电路，以响应于至少一个系统锁存信号和至少一个阴影锁存信号来提供数据输出信号。

7. 发明授权

US09551741B2 Current tests for I/O interface connectors 有权
标题翻译：当前测试I / O接口连接器
公开(公告)号：US09551741B2
公开(公告)日：2017-01-24
申请号：US13977648
申请日：2011-11-23
申请人： Bharani Thiruvengadam , Mladenko Vukic , Tak M. Mak
发明人： Bharani Thiruvengadam , Mladenko Vukic , Tak M. Mak
IPC分类号： G01R31/26 , G01R31/30 , G01R31/317 , G01R35/00
CPC分类号： G01R31/2607 , G01R31/3008 , G01R31/31716 , G01R35/005
摘要： Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.
摘要翻译：描述了I / O接口连接器的当前测试。在一个示例中，测试可以包括将强制能量施加到管芯上的集成电路的数据通信总线的接口的第一引脚，感测由接口的第二引脚处的强制能量引起的能量，强制能量和感测到的能量来确定由界面的至少一部分泄漏的电流量。

8. 发明授权

US09110134B2 Input/output delay testing for devices utilizing on-chip delay generation 有权
标题翻译：使用片上延迟生成的器件的输入/输出延迟测试
公开(公告)号：US09110134B2
公开(公告)日：2015-08-18
申请号：US13728741
申请日：2012-12-27
申请人： Tak M. Mak , Christopher J. Nelson , David J. Zimmerman , Derek B. Feltham
发明人： Tak M. Mak , Christopher J. Nelson , David J. Zimmerman , Derek B. Feltham
IPC分类号： G01R31/30 , G01R31/317
CPC分类号： G01R31/31716 , G01R31/3016
摘要： I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.
摘要翻译：利用片上延迟生成的器件进行I / O延迟测试。装置的实施例包括I / O缓冲电路，缓冲电路中的至少一个包括被耦合用于缓冲电路的环回测试的发射机和接收机; 以及用于所述至少一个缓冲电路的环回测试的测试电路，所述环回测试包括确定由所述缓冲器电路的发射机发送的测试数据是否与由所述相应耦合的接收机接收的测试数据相匹配。测试电路包括延迟线，用于从用于测试至少一个缓冲电路的发射时钟信号提供延迟值，提供计数以选择多个延迟值中的一个的计数器，回测试。

9. 发明授权

US07188284B2 Error detecting circuit 失效
标题翻译：错误检测电路
公开(公告)号：US07188284B2
公开(公告)日：2007-03-06
申请号：US10882523
申请日：2004-06-30
申请人： Subhasish Mitra , Kee S. Kim , Tak M. Mak , Prashant M. Goteti
发明人： Subhasish Mitra , Kee S. Kim , Tak M. Mak , Prashant M. Goteti
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31816 , G01R31/318566 , G11C2029/3202
摘要： In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.
摘要翻译：在一个实施例中，一种装置包括数据路径电路，用于响应于数据输入信号和至少第一数据时钟信号而产生数据输出信号; 阴影电路，耦合到数据路径电路，以在功能操作模式期间响应于数据输入信号和至少第二数据时钟信号产生阴影输出信号，并且响应于扫描信号产生扫描输出信号，在测试操作模式期间的信号和至少第一测试时钟信号; 以及耦合到数据路径和阴影电路的误差检测电路，以响应于数据输出信号和阴影输出信号之间的失配而产生误差信号。

10. 发明授权

US5621739A Method and apparatus for buffer self-test and characterization 失效
标题翻译：用于缓冲区自检和表征的方法和装置
公开(公告)号：US5621739A
公开(公告)日：1997-04-15
申请号：US643954
申请日：1996-05-07
申请人： Christopher J. Sine , Alper Ilkbahar , Tak M. Mak
发明人： Christopher J. Sine , Alper Ilkbahar , Tak M. Mak
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/31716 , G01R31/30 , G01R31/318577
摘要： A self-testing buffer circuit. The buffer circuit utilizes an adjustable delay circuit to test whether the buffer can capture a data value during a variable stroke window. The buffer includes an input circuit coupled to receive a data value generated by the self-testing buffer circuit. The buffer circuit also includes a latch which has a latch input coupled to receive the data value from the input circuit. An adjustable delay circuit having a delay adjust input is coupled to provide an adjustably delayed strobe to a clock input of the latch. A comparison circuit may be coupled to compare a latch output value to an expected value. The self-testing buffer circuit may be used in conjunction with serial or parallel test resisters to test the buffer performance for a variety of strobe delays and data values.
摘要翻译：自检缓冲电路。缓冲电路利用可调延迟电路来测试缓冲器是否可以在可变行程窗口期间捕获数据值。缓冲器包括耦合以接收由自测试缓冲器电路产生的数据值的输入电路。缓冲电路还包括锁存器，其具有耦合以从输入电路接收数据值的锁存器输入。具有延迟调整输入的可调延迟电路被耦合以向锁存器的时钟输入提供可调节延迟的选通。可以将比较电路耦合以将锁存器输出值与预期值进行比较。自测试缓冲电路可以与串行或并行测试电阻一起使用，以测试各种选通延迟和数据值的缓冲器性能。

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