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1. 发明授权

US09390913B2 Semiconductor dielectric interface and gate stack 有权
标题翻译：半导体介质接口和栅极叠层
公开(公告)号：US09390913B2
公开(公告)日：2016-07-12
申请号：US13774852
申请日：2013-02-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Hsun Wang , Shih Wei Wang , Ravi Droopad , Gerben Doombos , Georgios Vellianitis , Matthias Passlack
IPC分类号： H01L21/02 , H01L29/51 , H01L21/306 , H01L21/28
CPC分类号： H01L21/02304 , H01L21/02181 , H01L21/02312 , H01L21/28167 , H01L21/306 , H01L29/511 , H01L29/513 , H01L29/518
摘要： A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of the substrate; and depositing a dielectric layer above the termination layer, the depositing configured to not disrupt the termination layer. The forming of the termination layer may be configured to produce the termination layer having a single layer of oxygen atoms between the substrate and the dielectric layer.
摘要翻译：公开了一种具有降低的界面陷阱密度的半导体/介质接口和制造该接口的方法。在示例性实施例中，该方法包括接收衬底，所述衬底包含半导体; 制备基材的表面; 在所述基板的表面形成与所述半导体结合的端接层; 以及在所述终止层上方沉积介电层，所述沉积配置成不中断所述终止层。终端层的形成可以被配置为在衬底和电介质层之间产生具有单层氧原子层的端接层。

2. 发明申请

US20150171083A1 METHOD FOR ADJUSTING FIN WIDTH IN INTEGRATED CIRCUITRY 有权
标题翻译：用于调整集成电路中的宽度的方法
公开(公告)号：US20150171083A1
公开(公告)日：2015-06-18
申请号：US14104744
申请日：2013-12-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chien-Hsun Wang , Chih-Sheng Chang , Yi-Tang Lin
IPC分类号： H01L27/088 , H01L29/10
CPC分类号： H01L27/0886 , H01L21/823431 , H01L29/1037 , H01L29/66795 , H01L29/785
摘要： A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.
摘要翻译：一种方法包括在半导体衬底的表面上生长多个平行心轴，每个心轴具有至少两个横向相对的侧壁和预定宽度。该方法还包括在心轴的侧壁上形成第一类型的间隔物，其中两个相邻心轴之间的第一类型的间隔物被间隙分开。调整预定的心轴宽度以封闭相邻的第一类型间隔件之间的间隙，以形成第二类型的间隔件。去除心轴以形成第一类型的间隔件的第一类型的翅片，并且在两个相邻的心轴之间从间隔件形成第二类型的翅片。翅片的第二种类型比第一种翅片宽。

3. 发明授权

US10693003B2 Integrated circuit transistor structure with high germanium concentration SiGe stressor 有权
公开(公告)号：US10693003B2
公开(公告)日：2020-06-23
申请号：US15600311
申请日：2017-05-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chih-Hao Chang , Jeff J. Xu , Chien-Hsun Wang , Chih Chieh Yeh , Chih-Hsiang Chang
IPC分类号： H01L29/78 , H01L29/165 , H01L29/66 , H01L29/161 , H01L21/18 , H01L21/02 , H01L29/10
摘要： An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.

4. 发明授权

US09026959B2 Method and device for increasing fin device density for unaligned fins 有权
标题翻译：用于增加未对准翅片翅片装置密度的方法和装置
公开(公告)号：US09026959B2
公开(公告)日：2015-05-05
申请号：US14334195
申请日：2014-07-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Hsun Wang , Chih-Sheng Chang , Yi-Tang Lin , Ming-Feng Shieh
IPC分类号： G06F17/50 , H01L29/66 , G03F1/00
CPC分类号： G06F17/5072 , G03F1/00 , G06F17/5068 , H01L29/66795
摘要： A semiconductor manufacturing method of generating a layout for a device includes defining a first plurality of mandrels in a first active region of a first layout. Each mandrel of the first plurality of mandrels extends in a first direction and being spaced apart in a second direction perpendicular to the first direction. The method further includes defining a second plurality of mandrels in a second active region of the first layout. Each mandrel of the second plurality of mandrels extends in the first direction and being spaced apart in the second direction. An edge of the first active region is spaced from an edge of the second active region by a minimum distance less than a specified minimum spacing. The method further includes connecting, using a layout generator, at least one mandrel of the first plurality of mandrels to a corresponding mandrel of the second plurality of mandrels.
摘要翻译：产生装置的布局的半导体制造方法包括在第一布局的第一有源区中限定第一多个心轴。第一多个心轴的每个心轴在第一方向上延伸并且在垂直于第一方向的第二方向上间隔开。该方法还包括在第一布局的第二活动区域中限定第二多个心轴。第二多个心轴的每个心轴在第一方向上延伸并且在第二方向上间隔开。第一有源区域的边缘与第二有源区域的边缘间隔小于指定的最小间隔的最小距离。该方法还包括使用布局发生器将第一多个心轴中的至少一个心轴连接到第二多个心轴的对应心轴。

5. 发明申请

US20140239418A1 Semiconductor Dielectric Interface and Gate Stack 有权
标题翻译：半导体介质接口和栅极堆叠
公开(公告)号：US20140239418A1
公开(公告)日：2014-08-28
申请号：US13774852
申请日：2013-02-22
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chien-Hsun Wang , Shih Wei Wang , Ravi Droopad , Gerben Doombos , Georgios Vellianitis , Matthias Passlack
IPC分类号： H01L21/02 , H01L29/51
CPC分类号： H01L21/02304 , H01L21/02181 , H01L21/02312 , H01L21/28167 , H01L21/306 , H01L29/511 , H01L29/513 , H01L29/518
摘要： A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of the substrate; and depositing a dielectric layer above the termination layer, the depositing configured to not disrupt the termination layer. The forming of the termination layer may be configured to produce the termination layer having a single layer of oxygen atoms between the substrate and the dielectric layer.
摘要翻译：公开了一种具有降低的界面陷阱密度的半导体/介质接口和制造该接口的方法。在示例性实施例中，该方法包括接收衬底，所述衬底包含半导体; 制备基材的表面; 在所述基板的表面形成与所述半导体结合的端接层; 以及在所述终止层上方沉积介电层，所述沉积配置成不中断所述终止层。终端层的形成可以被配置为在衬底和电介质层之间产生具有单层氧原子层的端接层。

6. 发明授权

US09660082B2 Integrated circuit transistor structure with high germanium concentration SiGe stressor 有权
公开(公告)号：US09660082B2
公开(公告)日：2017-05-23
申请号：US14102702
申请日：2013-12-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chih-Hao Chang , Jeff J. Xu , Chien-Hsun Wang , Chih Chieh Yeh , Chih-Hsiang Chang
IPC分类号： H01L29/78 , H01L29/165 , H01L29/66 , H01L21/02 , H01L29/10
CPC分类号： H01L29/785 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/18 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/66795 , H01L29/7848
摘要： An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.

7. 发明授权

US09646823B2 Semiconductor dielectric interface and gate stack 有权
公开(公告)号：US09646823B2
公开(公告)日：2017-05-09
申请号：US14464434
申请日：2014-08-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Hsun Wang , Shih-Wei Wang , Gerben Doornbos , Georgios Vellianitis , Matthias Passlack
IPC分类号： H01L21/02 , H01L21/28 , H01L29/51 , H01L21/306 , H01L29/66 , H01L29/78
CPC分类号： H01L21/02304 , H01L21/02181 , H01L21/02312 , H01L21/28264 , H01L21/306 , H01L29/513 , H01L29/517 , H01L29/66522 , H01L29/78
摘要： A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer.

8. 发明授权

US09472550B2 Adjusted fin width in integrated circuitry 有权
标题翻译：集成电路中调整的散热片宽度
公开(公告)号：US09472550B2
公开(公告)日：2016-10-18
申请号：US14104744
申请日：2013-12-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chien-Hsun Wang , Chih-Sheng Chang , Yi-Tang Lin
IPC分类号： H01L21/84 , H01L27/088 , H01L27/12 , H01L29/06 , H01L29/10 , H01L21/8234
CPC分类号： H01L27/0886 , H01L21/823431 , H01L29/1037 , H01L29/66795 , H01L29/785
摘要： A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.
摘要翻译：一种方法包括在半导体衬底的表面上生长多个平行心轴，每个心轴具有至少两个横向相对的侧壁和预定宽度。该方法还包括在心轴的侧壁上形成第一类型的间隔物，其中两个相邻心轴之间的第一类型的间隔物被间隙分开。调整预定的心轴宽度以封闭相邻的第一类型间隔件之间的间隙，以形成第二类型的间隔件。去除心轴以形成第一类型的间隔件的第一类型的翅片，并且在两个相邻的心轴之间从间隔件形成第二类型的翅片。翅片的第二种类型比第一种翅片宽。

9. 发明授权

US08806397B2 Method and device for increasing fin device density for unaligned fins 有权
标题翻译：用于增加未对准翅片翅片装置密度的方法和装置
公开(公告)号：US08806397B2
公开(公告)日：2014-08-12
申请号：US14018133
申请日：2013-09-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Hsun Wang , Chih-Sheng Chang , Yi-Tang Lin , Ming-Feng Shieh
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F1/00 , G06F17/5068 , H01L29/66795
摘要： A method of generating a layout for a device includes receiving a first layout including a plurality of active regions, each active region of the plurality of active regions having sides. The method further includes defining a plurality of elongate mandrels that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction. The method further includes for each adjacent pair of partially-parallel active regions of the plurality of active regions having a minimum distance less than a specified minimum spacing, connecting at least a portion of nearest ends of pairs of elongate mandrels, each mandrel of a pair from a different active region. The method further includes generating a second layout including a plurality of elongate mandrels in the plurality of active regions, and connective elements between active regions of at least one adjacent pair of active regions.
摘要翻译：产生装置的布局的方法包括接收包括多个有效区域的第一布局，所述多个有源区域中的每个有源区域具有边。该方法还包括限定多个细长心轴，每个细长心轴在第一方向上延伸并且在垂直于第一方向的第二方向上彼此间隔开。该方法还包括对于多个有源区域中的每个相邻的一对部分平行的有源区域具有小于规定的最小间隔的最小距离，连接成对细长心轴的最近端的至少一部分，一对的每个心轴来自不同的活跃区域。该方法还包括产生包括多个有源区域中的多个细长心轴的第二布局，以及至少一个相邻的一对有源区域的有源区域之间的连接元件。

10. 发明申请

US20140353771A1 Semiconductor Dielectric Interface and Gate Stack 有权
标题翻译：半导体介质接口和栅极堆叠
公开(公告)号：US20140353771A1
公开(公告)日：2014-12-04
申请号：US14464434
申请日：2014-08-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Hsun Wang , Shih-Wei Wang , Gerben Doornbos , Georgios Vellianitis , Matthias Passlack
IPC分类号： H01L29/51 , H01L21/28 , H01L21/02
CPC分类号： H01L21/02304 , H01L21/02181 , H01L21/02312 , H01L21/28264 , H01L21/306 , H01L29/513 , H01L29/517 , H01L29/66522 , H01L29/78
摘要： A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer.
摘要翻译：公开了一种具有降低的界面陷阱密度的半导体/介质接口和制造该接口的方法。在示例性实施例中，形成半导体器件的方法包括接收衬底并在衬底的顶表面上形成端接层。终止层包括氢，氘或氮中的至少一种。该方法还包括在终端层上沉积介电层，使得介电层的沉积不会破坏端接层。终端层可以通过沉积终止层的第一材料的第一沉积工艺和后续的沉积工艺形成，该沉积工艺将端接层的第二材料引入第一材料中。端接层也可以通过沉积终端层的第一材料和第二材料的单一沉积工艺形成。

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