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1. 发明授权

US6107143A Method for forming a trench isolation structure in an integrated circuit 有权
标题翻译：在集成电路中形成沟槽隔离结构的方法
公开(公告)号：US6107143A
公开(公告)日：2000-08-22
申请号：US150668
申请日：1998-09-10
申请人： Tai-Su Park , Han-Sin Lee , Yu-Gyun Shin
发明人： Tai-Su Park , Han-Sin Lee , Yu-Gyun Shin
IPC分类号： H01L21/76 , H01L21/762 , H01L27/08
CPC分类号： H01L21/76232
摘要： A method is provided for forming a trench isolation structure in an integrated circuit that has a better reliability and an acceptable time-dependent dielectric breakdown over a greater range of production. The manufacturing method involves etching a trench in a semiconductor substrate, forming a sidewall-insulating layer along the sidewall and bottom of the trench, and depositing a trench-insulating layer in the trench and over the semiconductor substrate. The sidewall-insulating layer is formed to have a lower etch rate than the trench-insulating layer. As a result of this difference in etch rates, the sidewall-insulating layer is not damaged too much during wet etching processes that take place during the later part of manufacture. This makes the interface between the substrate, sidewall-insulating layer, and gate oxide more reliable. The difference in etching rate can be obtained by keeping an annealing process used in later processing below a threshold temperature so that the etch rate of the trench-isolating layer does fall too low. The difference in etching rate can also be obtained by using different materials for the sidewall-isolating layer and the trench-isolating layer, or by using multiple annealing processes.
摘要翻译：提供了一种用于在集成电路中形成沟槽隔离结构的方法，该集成电路在更大的生产范围内具有更好的可靠性和可接受的时间依赖介电击穿。该制造方法包括蚀刻半导体衬底中的沟槽，沿着沟槽的侧壁和底部形成侧壁绝缘层，并且在沟槽中和半导体衬底上沉积沟槽绝缘层。侧壁绝缘层形成为具有比沟槽绝缘层低的蚀刻速率。由于这种蚀刻速率的差异，在制造后期部分的湿式蚀刻工艺期间，侧壁绝缘层不会受到太大损害。这使得衬底，侧壁绝缘层和栅极氧化物之间的界面更可靠。通过将后续处理中使用的退火处理保持在阈值温度以下，使得沟槽隔离层的蚀刻速率确实降低，可以获得蚀刻速率的差异。也可以通过使用用于侧壁隔离层和沟槽隔离层的不同材料或通过使用多个退火工艺来获得蚀刻速率的差异。

2. 发明授权

US6083808A Method for forming a trench isolation in a semiconductor device 有权
标题翻译：在半导体器件中形成沟槽隔离的方法
公开(公告)号：US6083808A
公开(公告)日：2000-07-04
申请号：US160094
申请日：1998-09-25
申请人： Yu-Gyun Shin , Han-Sin Lee , Tai-su Park , Moon-Han Park
发明人： Yu-Gyun Shin , Han-Sin Lee , Tai-su Park , Moon-Han Park
IPC分类号： H01L21/76 , H01L21/28 , H01L21/762
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A method for forming a trench isolation in a semiconductor device is provided in which a first heat treatment process is conducted on a thermal oxide layer previously formed in a trench at temperature range from about 1000.degree. C. to 1200.degree. C. for about 1 to 8 hours so as to remove defects in a semiconductor substrate and oxygen impurities within the semiconductor substrate resulting from a step of forming the trench in the semiconductor substrate. As a result, a subsequent second heat treatment process for densifying a trench filling material such as a CVD oxide layer can be performed at lower temperature of about 1000.degree. C. to 1050.degree. C., as compared with the temperature of the first annealing of the thermal oxide layer, thereby reducing distortions of the semiconductor substrate and reducing current leakages.
摘要翻译：提供了一种在半导体器件中形成沟槽隔离的方法，其中对预先形成在沟槽中的热氧化层进行第一热处理工艺，温度范围为约1000℃至1200℃，约1至 8小时，以便从半导体衬底中形成沟槽的步骤得到半导体衬底中的缺陷和半导体衬底内的氧杂质。结果，与在第一次退火温度相比，可以在约1000℃至1050℃的较低温度下进行用于致密化CVD氧化物层的沟槽填充材料的随后的第二热处理工艺热氧化层，从而减少半导体衬底的变形并减少电流泄漏。

3. 发明授权

US06855590B2 Method of manufacturing the semiconductor device intended to prevent a leakage current from occuring due to a gate induced drain leakage effect 有权
标题翻译：制造半导体器件的方法，旨在防止由于栅极引起的漏极泄漏效应引起的漏电流的发生
公开(公告)号：US06855590B2
公开(公告)日：2005-02-15
申请号：US10650089
申请日：2003-08-28
申请人： Sang-Hun Seo , Seung-Hyun Park , Han-Sin Lee , Moo-Sung Kim , Won-Suk Yang
发明人： Sang-Hun Seo , Seung-Hyun Park , Han-Sin Lee , Moo-Sung Kim , Won-Suk Yang
IPC分类号： H01L27/092 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/108 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/2652 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/6659
摘要： A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.
摘要翻译：降低了栅极感应漏极泄漏（GIDL）效应的CMOS半导体器件及其制造方法。在本发明的半导体器件中，PMOS晶体管的高浓度源极/漏极区远离栅极图案侧壁间隔物形成。这是通过使用形成在半导体衬底的整个表面上的电介质膜作为注入掩模来实现的，其中半导体衬底包括n阱中的PMOS晶体管区域，由PMOS晶体管形成的PMOS晶体管的低浓度源极/漏极区域使用栅极图案作为注入掩模，PMOS晶体管栅极图案侧壁间隔物以及NMOS阱中的NMOS晶体管区域，NMOS晶体管具有低浓度和高浓度源极/漏极区域。

4. 发明申请

US20100163823A1 RESISTIVE RANDOM ACCESS MEMORY 有权
标题翻译：电阻随机存取存储器
公开(公告)号：US20100163823A1
公开(公告)日：2010-07-01
申请号：US12649413
申请日：2009-12-30
申请人： Hyun-Jun Sim , Han-Sin Lee , In-Gyu Baek , Jinshi Zhao , Eun-Kyung Yim
发明人： Hyun-Jun Sim , Han-Sin Lee , In-Gyu Baek , Jinshi Zhao , Eun-Kyung Yim
IPC分类号： H01L47/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0071 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/55 , G11C2213/77 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要： A resistive memory device includes a first electrode, a resistive oxidation structure and a second electrode. The resistive oxidation structure has sets of oxidation layers stacked on the first electrode. Each set is made up of a first metal oxide layer and a second metal oxide layer which is disposed on and is thinner than the first metal oxide layer. The first metal oxidation layer of the first one of the sets of oxidation layers contacts an upper surface of the first electrode. The second electrode is formed on the resistive oxidation structure. The resistance of the oxidation structure can be changed by an electric field
摘要翻译：电阻式存储器件包括第一电极，电阻氧化结构和第二电极。电阻氧化结构具有堆叠在第一电极上的一组氧化层。每组由第一金属氧化物层和设置在第一金属氧化物层上且比第一金属氧化物层薄的第二金属氧化物层组成。第一组氧化层中的第一金属氧化层接触第一电极的上表面。第二电极形成在电阻氧化结构上。氧化结构的电阻可以通过电场来改变

5. 发明申请

US20070181882A1 Multi-level semiconductor device and method of fabricating the same 有权
标题翻译：多级半导体器件及其制造方法
公开(公告)号：US20070181882A1
公开(公告)日：2007-08-09
申请号：US11703649
申请日：2007-02-08
申请人： Han-Sin Lee
发明人： Han-Sin Lee
IPC分类号： H01L29/10
CPC分类号： H01L27/0688 , H01L21/8221 , H01L27/11 , H01L27/1108
摘要： A multi-level semiconductor device includes a first transistor on a semiconductor substrate, the first transistor including a first source/drain region, a semiconductor layer on the semiconductor substrate, a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer, and a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.
摘要翻译：多级半导体器件包括半导体衬底上的第一晶体管，第一晶体管包括第一源/漏区，半导体衬底上的半导体层，半导体层上的第二晶体管，第二晶体管包括第二源/ 漏极区域，以及从所述第一源极/漏极区域延伸并接触所述半导体层的第二部分的接触图案，其中所述半导体层的所述第二部分具有大于所述半导体层的第二部分的杂质浓度的第二源极/漏极区域。

6. 发明授权

US08148765B2 Resistive random access memory 有权
标题翻译：电阻随机存取存储器
公开(公告)号：US08148765B2
公开(公告)日：2012-04-03
申请号：US12649413
申请日：2009-12-30
申请人： Hyun-Jun Shim , Han-Sin Lee , In-Gyu Baek , Jinshi Zhao , Eun-Kyung Yim
发明人： Hyun-Jun Shim , Han-Sin Lee , In-Gyu Baek , Jinshi Zhao , Eun-Kyung Yim
IPC分类号： H01L27/108
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0071 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/55 , G11C2213/77 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要： A resistive memory device includes a first electrode, a resistive oxidation structure and a second electrode. The resistive oxidation structure has sets of oxidation layers stacked on the first electrode. Each set is made up of a first metal oxide layer and a second metal oxide layer which is disposed on and is thinner than the first metal oxide layer. The first metal oxidation layer of the first one of the sets of oxidation layers contacts an upper surface of the first electrode. The second electrode is formed on the resistive oxidation structure. The resistance of the oxidation structure can be changed by an electric field.
摘要翻译：电阻式存储器件包括第一电极，电阻氧化结构和第二电极。电阻氧化结构具有堆叠在第一电极上的一组氧化层。每组由第一金属氧化物层和设置在第一金属氧化物层上且比第一金属氧化物层薄的第二金属氧化物层组成。第一组氧化层中的第一金属氧化层接触第一电极的上表面。第二电极形成在电阻氧化结构上。氧化结构的电阻可以通过电场来改变。

7. 发明申请

US20050151173A1 Semiconductor device and methods of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050151173A1
公开(公告)日：2005-07-14
申请号：US11022809
申请日：2004-12-28
申请人： Sang-Hun Seo , Seung-Hyun Park , Han-Sin Lee , Moo-Sung Kim , Won-Suk Yang
发明人： Sang-Hun Seo , Seung-Hyun Park , Han-Sin Lee , Moo-Sung Kim , Won-Suk Yang
IPC分类号： H01L27/092 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/108 , H01L29/76 , H01L29/78
CPC分类号： H01L21/2652 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/6659 , H01L29/7833
摘要： A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.
摘要翻译：降低了栅极感应漏极泄漏（GIDL）效应的CMOS半导体器件及其制造方法。在本发明的半导体器件中，PMOS晶体管的高浓度源极/漏极区远离栅极图案侧壁间隔物形成。这是通过使用形成在半导体衬底的整个表面上的电介质膜作为注入掩模来实现的，其中半导体衬底包括n阱中的PMOS晶体管区域，由PMOS晶体管形成的PMOS晶体管的低浓度源极/漏极区域使用栅极图案作为注入掩模，PMOS晶体管栅极图案侧壁间隔物以及NMOS阱中的NMOS晶体管区域，NMOS晶体管具有低浓度和高浓度源极/漏极区域。

8. 发明授权

US07947540B2 Multi-level semiconductor device and method of fabricating the same 有权
标题翻译：多级半导体器件及其制造方法
公开(公告)号：US07947540B2
公开(公告)日：2011-05-24
申请号：US11703649
申请日：2007-02-08
申请人： Han-Sin Lee
发明人： Han-Sin Lee
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/0688 , H01L21/8221 , H01L27/11 , H01L27/1108
摘要： A multi-level semiconductor device includes a first transistor on a semiconductor substrate, the first transistor including a first source/drain region, a semiconductor layer on the semiconductor substrate, a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer, and a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.
摘要翻译：多级半导体器件包括半导体衬底上的第一晶体管，第一晶体管包括第一源/漏区，半导体衬底上的半导体层，半导体层上的第二晶体管，第二晶体管包括第二源/ 漏极区域，以及从所述第一源极/漏极区域延伸并接触所述半导体层的第二部分的接触图案，其中所述半导体层的所述第二部分具有大于所述半导体层的第二部分的杂质浓度的第二源极/漏极区域。

9. 发明授权

US06875670B2 Trench isolation method 有权
标题翻译：沟槽隔离法
公开(公告)号：US06875670B2
公开(公告)日：2005-04-05
申请号：US09775231
申请日：2001-02-01
申请人： Han-Sin Lee , Moon-Han Park
发明人： Han-Sin Lee , Moon-Han Park
IPC分类号： H01L21/76 , H01L21/762 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76224
摘要： In a trench isolation method, an etching mask pattern for forming a trench is formed on a semiconductor substrate. The substrate is etched to form a trench. An insulating layer is formed to fill the trench, and then a material layer is formed on the insulating layer. In this case, the material layer is made of material formed at a high temperature to density the insulating layer. The material layer and the insulating layer are planarly etched and the etching mask pattern is removed, so that a trench isolation layer is completed. Accordingly, although a densification process is avoided, it is possible to form a device isolation layer having a favorable surface profile.
摘要翻译：在沟槽隔离方法中，在半导体衬底上形成用于形成沟槽的蚀刻掩模图案。蚀刻衬底以形成沟槽。形成绝缘层以填充沟槽，然后在绝缘层上形成材料层。在这种情况下，材料层由在高温下形成的材料制成，以密封绝缘层。平面蚀刻材料层和绝缘层，去除蚀刻掩模图案，从而完成沟槽隔离层。因此，尽管避免了致密化过程，但是可以形成具有良好表面轮廓的器件隔离层。

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