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1. 发明授权

US06836131B2 Spray cooling and transparent cooling plate thermal management system 有权
公开(公告)号：US06836131B2
公开(公告)日：2004-12-28
申请号：US10379925
申请日：2003-03-04
申请人： Tahir Cader , Nathan Stoddard , Donald Tilton , Nader Pakdaman , Steven Kasapi
发明人： Tahir Cader , Nathan Stoddard , Donald Tilton , Nader Pakdaman , Steven Kasapi
IPC分类号： G01R3128
CPC分类号： G01R31/2875 , G01R1/0458 , G01R31/2891
摘要： A combination cooling plate and micro-spray cooling system beneficial for use in testers of electrically stimulated integrated circuit chips is disclosed. The system includes a transparent heat spreader and micro-spray heads disposed about the heat spreader. The spray heads spray cooling liquid onto a periphery of said heat spreader so as to remove heat from the chip. Alternatively, and micro-spray heads are provided inside the cooling plate holder so as to spray cooling liquid inside the interior of the holder so that the holder is cooled. The holder is in physical contact with the heat spreader, so that as the holder is cooled by the spray, heat is removed from the heat spreader, and thereby from the chip.

2. 发明授权

US06859031B2 Apparatus and method for dynamic diagnostic testing of integrated circuits 失效
标题翻译：集成电路动态诊断测试装置及方法
公开(公告)号：US06859031B2
公开(公告)日：2005-02-22
申请号：US10229181
申请日：2002-08-26
申请人： Nader Pakdaman , Steven Kasapi , Itzik Goldberger
发明人： Nader Pakdaman , Steven Kasapi , Itzik Goldberger
IPC分类号： G01R1/06 , G01R31/302 , G01R31/311 , G01R31/3185 , H01L21/66 , G01N27/72
CPC分类号： G01R31/318505 , G01R31/311 , G01R31/318511
摘要： Systems and methods consistent with principles of the present invention allow contactless measuring of various kinds of electrical activity within an integrated circuit. The invention can be used for high-bandwidth, at speed testing of various devices on a wafer during the various stages of device processing, or on packaged parts at the end of the manufacturing cycle. Power is applied to the test circuit using conventional mechanical probes or other means, such as CW laser light applied to a photoreceiver provided on the test circuit. The electrical test signal is introduced into the test circuit by stimulating the circuit using a contactless method, such as by directing the output of one or more modelocked lasers onto high-speed receivers on the circuit, or by using a high-speed pulsed diode laser. The electrical activity within the circuit in response to the test signal is sensed by a receiver element, such as a time-resolved photon counting detector, a static emission camera system, or by an active laser probing system. The collected information is used for a variety of purposes, including manufacturing process monitoring, new process qualification, and model verification.
摘要翻译：与本发明的原理一致的系统和方法允许在集成电路内的各种电活动的非接触式测量。本发明可以用于在器件处理的各个阶段期间的晶片上的各种器件的高带宽，速度测试，或者在制造周期结束时的封装部件上。使用传统的机械探针或其他手段（例如施加到设置在测试电路上的光接收器的CW激光）将功率施加到测试电路。电测试信号通过使用非接触方法来刺激电路而被引入到测试电路中，例如通过将一个或多个锁模激光器的输出引导到电路上的高速接收器上，或者通过使用高速脉冲二极管激光器。响应于测试信号的电路内的电活动由诸如时间分辨光子计数检测器，静态发射照相机系统或主动激光探测系统的接收器元件感测。收集的信息用于各种目的，包括制造过程监控，新工艺认证和型号验证。

3. 发明申请

US20060103378A1 Apparatus and method for dynamic diagnostic testing of integrated circuits 审中-公开
标题翻译：集成电路动态诊断测试装置及方法
公开(公告)号：US20060103378A1
公开(公告)日：2006-05-18
申请号：US10986480
申请日：2004-11-12
申请人： Nader Pakdaman , Steven Kasapi , Itzik Goldberger
发明人： Nader Pakdaman , Steven Kasapi , Itzik Goldberger
IPC分类号： G01R33/12
CPC分类号： G01R31/311 , G01R31/2831 , G01R31/2884
摘要： Systems and methods consistent with principles of the present invention allow contactless measuring of various kinds of electrical activity within an integrated circuit. The invention can be used for high-bandwidth, at speed testing of various devices on a wafer during the various stages of device processing, or on packaged parts at the end of the manufacturing cycle. Power is applied to the test circuit using conventional mechanical probes or other means, such as CW laser light applied to a photoreceiver provided on the test circuit. The electrical test signal is introduced into the test circuit by stimulating the circuit using a contactless method, such as by directing the output of one or more modelocked lasers onto high-speed receivers on the circuit, or by using a high-speed pulsed diode laser. The electrical activity within the circuit in response to the test signal is sensed by a receiver element, such as a time-resolved photon counting detector, a static emission camera system, or by an active laser probing system. The collected information is used for a variety of purposes, including manufacturing process monitoring, new process qualification, and model verification.
摘要翻译：与本发明的原理一致的系统和方法允许在集成电路内的各种电活动的非接触式测量。本发明可以用于在器件处理的各个阶段期间的晶片上的各种器件的高带宽，速度测试，或者在制造周期结束时的封装部件上。使用传统的机械探针或其他手段（例如施加到设置在测试电路上的光接收器的CW激光）将功率施加到测试电路。电测试信号通过使用非接触方法来刺激电路而被引入到测试电路中，例如通过将一个或多个锁模激光器的输出引导到电路上的高速接收器上，或者通过使用高速脉冲二极管激光器。响应于测试信号的电路内的电活动由诸如时间分辨光子计数检测器，静态发射照相机系统或主动激光探测系统的接收器元件感测。收集的信息用于各种目的，包括制造过程监控，新工艺认证和型号验证。

4. 发明申请

US20050090916A1 Intra-chip power and test signal generation for use with test structures on wafers 有权
标题翻译：片上功率和测试信号的产生，用于晶圆上的测试结构
公开(公告)号：US20050090916A1
公开(公告)日：2005-04-28
申请号：US10927406
申请日：2004-08-25
申请人： Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
发明人： Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , H01L21/66 , H01L23/544 , G06F17/00 , H01L21/301 , H01L21/46 , H01L21/78
CPC分类号： H01L22/20 , G01R31/2831 , G01R31/3025 , G01R31/31707 , G01R31/31718 , G01R31/318505 , G01R31/318511 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
摘要翻译：可以从晶片处于部分制造状态开始分析晶片的制造。可以在晶片的管芯的有效区域上的多个位置处确定指定性能参数的值。已知指定的性能参数指示制造中的特定制造工艺。然后可以基于多个位置处的性能参数的值的方差来获得评估信息。这可以在不影响从芯片产生的芯片的可用性的情况下完成。评价信息可以用于评估执行由性能参数值指示的包括特定制造过程的一个或多个处理。

5. 发明申请

US20050090027A1 System and apparatus for using test structures inside of a chip during the fabrication of the chip 有权
标题翻译：在芯片制造期间使用芯片内部的测试结构的系统和装置
公开(公告)号：US20050090027A1
公开(公告)日：2005-04-28
申请号：US10927258
申请日：2004-08-25
申请人： Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
发明人： Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , H01L21/66 , H01L23/544 , G01R31/26 , H01L21/301 , H01L21/46 , H01L21/78 , H01L23/58 , H01L29/10
CPC分类号： H01L22/20 , G01R31/2831 , G01R31/3025 , G01R31/31707 , G01R31/31718 , G01R31/318505 , G01R31/318511 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
摘要翻译：可以从晶片处于部分制造状态开始分析晶片的制造。可以在晶片的管芯的有效区域上的多个位置处确定指定性能参数的值。已知指定的性能参数指示制造中的特定制造工艺。然后可以基于多个位置处的性能参数的值的方差来获得评估信息。这可以在不影响从芯片产生的芯片的可用性的情况下完成。评价信息可以用于评估执行由性能参数值指示的包括特定制造过程的一个或多个处理。

6. 发明授权

US06594086B1 Bi-convex solid immersion lens 有权
公开(公告)号：US06594086B1
公开(公告)日：2003-07-15
申请号：US10052011
申请日：2002-01-16
申请人： Nader Pakdaman , James S. Vickers
发明人： Nader Pakdaman , James S. Vickers
IPC分类号： G02B2102
CPC分类号： G11B7/122 , B82Y10/00 , G02B3/00 , G02B3/02 , G11B7/1374 , G11B7/1378 , G11B7/1387 , G11B2007/13727 , H01L27/14625
摘要： A bi-convex solid immersion lens is disclosed. Unlike conventional plano-convex solid immersion lenses having a flat bottom surface, the disclosed lens has a convex bottom surface. The radius of curvature of the bottom surface is smaller than that of the object to be inspected. This construction allows for a more accurate determination of the location of the inspected feature, and enhances coupling of light between the immersion lens and the inspected object. The disclosed lens is particularly useful for use in microscope for inspection of semiconductor devices and, especially flip-chip (or chip scale) packaged devices. The immersion lens can also be incorporated in a read or read/write head of optical memory media.

7. 发明申请

US20080100319A1 INTRA-CHIP POWER AND TEST SIGNAL GENERATION FOR USE WITH TEST STRUCTURES ON WAFERS 有权
标题翻译：芯片功率和测试信号产生用于波形测试结构
公开(公告)号：US20080100319A1
公开(公告)日：2008-05-01
申请号：US11935297
申请日：2007-11-05
申请人： Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
发明人： Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
IPC分类号： G01R31/26
CPC分类号： H01L22/20 , G01R31/2831 , G01R31/3025 , G01R31/31707 , G01R31/31718 , G01R31/318505 , G01R31/318511 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
摘要翻译：可以从晶片处于部分制造状态开始分析晶片的制造。可以在晶片的管芯的有效区域上的多个位置处确定指定性能参数的值。已知指定的性能参数指示制造中的特定制造工艺。然后可以基于多个位置处的性能参数的值的方差来获得评估信息。这可以在不影响从芯片产生的芯片的可用性的情况下完成。评价信息可以用于评估执行由性能参数值指示的包括特定制造过程的一个或多个处理。

8. 发明申请

US20070238206A1 SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DURING THE FABRICATION OF THE CHIP 有权
公开(公告)号：US20070238206A1
公开(公告)日：2007-10-11
申请号：US11762944
申请日：2007-06-14
申请人： Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
发明人： Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , G01R31/2831 , G01R31/3025 , G01R31/31707 , G01R31/31718 , G01R31/318505 , G01R31/318511 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

9. 发明授权

US07256055B2 System and apparatus for using test structures inside of a chip during the fabrication of the chip 有权
标题翻译：在芯片制造期间使用芯片内部的测试结构的系统和装置
公开(公告)号：US07256055B2
公开(公告)日：2007-08-14
申请号：US10927258
申请日：2004-08-25
申请人： Majid Aghababazadeh , Jose J. Estabil , Nader Pakdaman , Gary L. Steinbrueck , James S. Vickers
发明人： Majid Aghababazadeh , Jose J. Estabil , Nader Pakdaman , Gary L. Steinbrueck , James S. Vickers
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , G01R31/2831 , G01R31/3025 , G01R31/31707 , G01R31/31718 , G01R31/318505 , G01R31/318511 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
摘要翻译：可以从晶片处于部分制造状态开始分析晶片的制造。可以在晶片的管芯的有效区域上的多个位置处确定指定性能参数的值。已知指定的性能参数指示制造中的特定制造工艺。然后可以基于多个位置处的性能参数的值的方差来获得评估信息。这可以在不影响从芯片产生的芯片的可用性的情况下完成。评价信息可以用于评估执行由性能参数值指示的包括特定制造过程的一个或多个处理。

10. 发明授权

US07227702B2 Bi-convex solid immersion lens 有权
标题翻译：双凸固体浸没透镜
公开(公告)号：US07227702B2
公开(公告)日：2007-06-05
申请号：US10883542
申请日：2004-07-01
申请人： Nader Pakdaman , James S. Vickers
发明人： Nader Pakdaman , James S. Vickers
IPC分类号： G02B21/00 , G02B21/02 , G02B13/18
CPC分类号： G11B7/122 , B82Y10/00 , G02B3/00 , G02B3/02 , G11B7/1374 , G11B7/1378 , G11B7/1387 , G11B2007/13727 , H01L27/14625
摘要： A bi-convex solid immersion lens is disclosed, having a top and bottom convex surfaces. The radius of curvature of the bottom surface is larger than that of the top surface. A conical sloped side-wall connects the top and bottom surface.
摘要翻译：公开了一种具有顶部和底部凸起表面的双凸型固体浸没透镜。底面的曲率半径大于上表面的曲率半径。锥形倾斜的侧壁连接顶部和底部表面。

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