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    • 2. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME
    • 薄膜晶体管阵列及其制造方法
    • US20080003728A1
    • 2008-01-03
    • US11619407
    • 2007-01-03
    • Tae-Hyung HWANGHyung-Il JEONNam-Seok ROHSang-Il KIM
    • Tae-Hyung HWANGHyung-Il JEONNam-Seok ROHSang-Il KIM
    • H01L21/84
    • H01L27/124H01L27/12H01L27/1214H01L27/1218H01L27/1288H01L29/78603
    • A thin film transistor array panel and a method of manufacturing the same include: forming a gate electrode on an insulating substrate; sequentially forming a gate insulating layer; a semiconductor material layer and an ohmic contact material layer on the gate electrode; forming a first semiconductor layer pattern and a first ohmic contact pattern for covering the gate electrode and a surrounding area of the gate electrode by patterning the semiconductor material layer and the ohmic contact material layer; forming a conductive film on the gate insulating layer and the first ohmic contact pattern; forming a conductive film pattern on a partial area of the first ohmic contact pattern and a data line on the gate insulating layer by patterning the conductive film; forming a second ohmic contact pattern and a second semiconductor layer pattern by sequentially etching the first ohmic contact pattern and the first semiconductor layer pattern exposed by deviating from the conductive film pattern; forming a source electrode and a drain electrode separated from each other by patterning the conductive film pattern; forming an ohmic contact by etching the second ohmic contact pattern exposed between the separated source electrode and drain electrode; and forming a pixel electrode connected to the drain electrode. Therefore, even if an insulating substrate expands due to heat, erroneous alignment is not generated between a projection of the semiconductor layer and the source electrode and the drain electrode, thereby improving manufacturing efficiency and performance of a thin film transistor array panel.
    • 薄膜晶体管阵列面板及其制造方法包括:在绝缘基板上形成栅电极; 依次形成栅极绝缘层; 栅电极上的半导体材料层和欧姆接触材料层; 通过图案化所述半导体材料层和所述欧姆接触材料层,形成第一半导体层图案和第一欧姆接触图案,以覆盖所述栅电极和所述栅电极的周围区域; 在所述栅极绝缘层和所述第一欧姆接触图案上形成导电膜; 通过图案化导电膜,在第一欧姆接触图案的部分区域和栅极绝缘层上的数据线上形成导电膜图案; 通过依次蚀刻通过偏离导电膜图案而暴露的第一欧姆接触图案和第一半导体层图案,形成第二欧姆接触图案和第二半导体层图案; 通过图案化所述导电膜图案来形成彼此分离的源电极和漏电极; 通过蚀刻暴露在分离的源电极和漏极之间的第二欧姆接触图形来形成欧姆接触; 以及形成连接到所述漏电极的像素电极。 因此,即使绝缘基板由于热而膨胀,也不会在半导体层的突起与源电极和漏电极之间产生错误对准,从而提高薄膜晶体管阵列面板的制造效率和性能。