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1. 发明授权

US08283248B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08283248B2
公开(公告)日：2012-10-09
申请号：US13234558
申请日：2011-09-16
申请人： Tae-Hyun Kim , Kyung-Hyun Kim , Jae-Hwang Sim , Jae-Jin Shin , Jong-Heun Lim , Hyun-Min Park
发明人： Tae-Hyun Kim , Kyung-Hyun Kim , Jae-Hwang Sim , Jae-Jin Shin , Jong-Heun Lim , Hyun-Min Park
IPC分类号： H01L21/4763
CPC分类号： H01L27/11526 , H01L21/764 , H01L21/7682 , H01L27/11529 , H01L27/11573
摘要： A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.
摘要翻译：一种制造半导体器件的方法包括：形成多个初步栅极结构，在多个预选栅极结构的侧壁上形成覆盖层图案，以及在多个预选栅极结构的顶表面上形成阻挡层，并且覆盖层使得它们之间形成空隙。该方法还包括去除阻挡层和覆盖层图案的上部，使得至少多个预选栅极结构的上侧壁被暴露，并且覆盖层图案的下部保留在预备的栅极结构的下侧壁上门结构。所述方法还包括在所述多个预选择门结构的至少上侧壁上形成导电层，使所述导电层与所述预选栅极结构反应，以及在其中形成具有气隙的绝缘层。

2. 发明申请

US20120070976A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120070976A1
公开(公告)日：2012-03-22
申请号：US13234558
申请日：2011-09-16
申请人： Tae-Hyun KIM , Kyung-Hyun Kim , Jae-Hwang Sim , Jae-Jin Shin , Jong-Heun Lim , Hyun-Min Park
发明人： Tae-Hyun KIM , Kyung-Hyun Kim , Jae-Hwang Sim , Jae-Jin Shin , Jong-Heun Lim , Hyun-Min Park
IPC分类号： H01L21/28
CPC分类号： H01L27/11526 , H01L21/764 , H01L21/7682 , H01L27/11529 , H01L27/11573
摘要： A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.
摘要翻译：一种制造半导体器件的方法包括：形成多个初步栅极结构，在多个预选栅极结构的侧壁上形成覆盖层图案，以及在多个预选栅极结构的顶表面上形成阻挡层，并且覆盖层使得它们之间形成空隙。该方法还包括去除阻挡层和覆盖层图案的上部，使得至少多个预选栅极结构的上侧壁被暴露，并且覆盖层图案的下部保留在预备的栅极结构的下侧壁上门结构。所述方法还包括在所述多个预选择门结构的至少上侧壁上形成导电层，使所述导电层与所述预选栅极结构反应，以及在其中形成具有气隙的绝缘层。

3. 发明申请

US20130065386A1 MULTIPLE MOLD STRUCTURE METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES 有权
标题翻译：制造垂直存储器件的多种模具结构方法
公开(公告)号：US20130065386A1
公开(公告)日：2013-03-14
申请号：US13596621
申请日：2012-08-28
申请人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
发明人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L27/11573 , H01L29/7926
摘要： A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.
摘要翻译：在包括第一和第二区域的基板上形成第一绝缘中间层。第一绝缘中间层具有顶表面，其高度在第一区域中大于在第二区域中的高度。形成第一平坦化停止层和第二绝缘夹层。平面化第二绝缘层，直到第一平坦化停止层露出。去除第二区域中的第一平坦化停止层和第一和第二绝缘夹层以露出衬底。形成包括第一绝缘层图案，第一牺牲层图案和第二平坦化停止层图案的下模具结构。第一绝缘层图案和第一牺牲层图案在基板上交替重复地形成，并且在第一绝缘层图案上形成第二平坦化停止层图案。

4. 发明授权

US09997534B2 Vertical memory devices 有权
公开(公告)号：US09997534B2
公开(公告)日：2018-06-12
申请号：US15155732
申请日：2016-05-16
申请人： Yong-Hoon Son , Kyung-Hyun Kim , Byeong-Ju Kim , Phil-Ouk Nam , Kwang Chul Park , Yeon-Sil Sohn , Jin-I Lee , Jong-Heun Lim , Won-Bong Jung , Kohji Kanamori
发明人： Yong-Hoon Son , Kyung-Hyun Kim , Byeong-Ju Kim , Phil-Ouk Nam , Kwang Chul Park , Yeon-Sil Sohn , Jin-I Lee , Jong-Heun Lim , Won-Bong Jung , Kohji Kanamori
IPC分类号： H01L29/792 , H01L27/11582 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/528
摘要： A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

5. 发明授权

US08822287B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08822287B2
公开(公告)日：2014-09-02
申请号：US13313754
申请日：2011-12-07
申请人： Hyo-Jung Kim , Ki-hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
发明人： Hyo-Jung Kim , Ki-hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
IPC分类号： H01L21/336
CPC分类号： H01L21/31053 , H01L21/3212 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.
摘要翻译：制造半导体器件的方法包括在第一区域中形成集成结构和第一停止层图案。形成第一绝缘层和第二阻挡层。通过部分蚀刻第一区域中的第二阻挡层和第一绝缘中间层来形成第二初步绝缘中间层。执行第一次抛光以去除突出部分。执行第二抛光以暴露第一和第二停止层图案。

6. 发明授权

US08664101B2 Multiple mold structure methods of manufacturing vertical memory devices 有权
标题翻译：制造垂直存储器件的多种模具结构方法
公开(公告)号：US08664101B2
公开(公告)日：2014-03-04
申请号：US13596621
申请日：2012-08-28
申请人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
发明人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11582 , H01L27/11573 , H01L29/7926
摘要： A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.
摘要翻译：在包括第一和第二区域的基板上形成第一绝缘中间层。第一绝缘中间层具有顶表面，其高度在第一区域中大于在第二区域中的高度。形成第一平坦化停止层和第二绝缘夹层。平面化第二绝缘层，直到第一平坦化停止层露出。去除第二区域中的第一平坦化停止层和第一和第二绝缘夹层以露出衬底。形成包括第一绝缘层图案，第一牺牲层图案和第二平坦化停止层图案的下模具结构。第一绝缘层图案和第一牺牲层图案在基板上交替重复地形成，并且在第一绝缘层图案上形成第二平坦化停止层图案。

7. 发明申请

US20120149185A1 Methods Of Manufacturing Semiconductor Devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120149185A1
公开(公告)日：2012-06-14
申请号：US13313754
申请日：2011-12-07
申请人： Hyo-Jung Kim , Ki-Hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
发明人： Hyo-Jung Kim , Ki-Hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
IPC分类号： H01L21/3205 , H01L21/311
CPC分类号： H01L21/31053 , H01L21/3212 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.
摘要翻译：制造半导体器件的方法包括在第一区域中形成集成结构和第一停止层图案。形成第一绝缘层和第二阻挡层。通过部分蚀刻第一区域中的第二阻挡层和第一绝缘中间层来形成第二初步绝缘中间层。执行第一次抛光以去除突出部分。执行第二抛光以暴露第一和第二停止层图案。

8. 发明申请

US20080164503A1 Ferroelectric Memory Devices Having a Protruding Bottom Electrode and Methods of Forming the Same 审中-公开
标题翻译：具有突起底电极的铁电存储器件及其形成方法
公开(公告)号：US20080164503A1
公开(公告)日：2008-07-10
申请号：US11970770
申请日：2008-01-08
申请人： Suk-Hun Choi , Chang-Ki Hong , Jung-Hyeon Kim , Jun-Young Lee , Jong-Heun Lim , Seong-Kyu Yun
发明人： Suk-Hun Choi , Chang-Ki Hong , Jung-Hyeon Kim , Jun-Young Lee , Jong-Heun Lim , Seong-Kyu Yun
IPC分类号： G11C11/22 , H01L29/78 , H01L21/02
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/82
摘要： A ferroelectric memory device and methods of forming the same are provided. Forming a ferroelectric device includes forming an insulation layer over a substrate having a conductive region, forming a bottom electrode electrically connected to the conductive region in the insulation layer, recessing the insulation layer, and forming a ferroelectric layer and an upper electrode layer covering the bottom electrode over the recessed insulation layer, The bottom electrode protrudes over an upper surface of the recessed insulation layer.
摘要翻译：提供了铁电存储器件及其形成方法。形成铁电体器件包括在具有导电区域的衬底上形成绝缘层，形成与绝缘层中的导电区域电连接的底部电极，使绝缘层凹陷，并形成覆盖底部的铁电层和上电极层电极在凹陷绝缘层上方，底部电极突出在凹陷绝缘层的上表面上。

9. 发明授权

US07678625B2 Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics 有权
标题翻译：制造半导体器件的方法包括具有改进的缺陷密度和表面粗糙度特性的沟道层
公开(公告)号：US07678625B2
公开(公告)日：2010-03-16
申请号：US11962742
申请日：2007-12-21
申请人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
发明人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
IPC分类号： H01L21/84
CPC分类号： H01L21/02675 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/78
摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.
摘要翻译：制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。单晶半导体层包括从其表面延伸的突起。在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。还讨论了制造叠层半导体存储器件的相关方法。

10. 发明申请

US20090098804A1 Apparatus for polishing a wafer and method for detecting a polishing end point by the same 有权
标题翻译：用于抛光晶片的装置和用于检测抛光终点的方法
公开(公告)号：US20090098804A1
公开(公告)日：2009-04-16
申请号：US12285852
申请日：2008-10-15
申请人： Jong-Heun Lim , Sung-Ho Shin , Bo-Un Yoon , Chang-Ki Hong
发明人： Jong-Heun Lim , Sung-Ho Shin , Bo-Un Yoon , Chang-Ki Hong
IPC分类号： B24B49/12 , B24B9/00 , B24B21/02
CPC分类号： B24B9/065 , B24B21/02 , B24B37/013 , B24B49/12
摘要： A wafer polishing apparatus includes a polishing tape extending between two guide rollers, a first surface of the polishing tape contacting a surface of a wafer to be polished, a polishing head including a pusher pad, the pusher pad adapted to push the polishing tape against the surface of the wafer to be polished, a color image sensor adjacent to the polishing tape, the color image sensor being adapted to detect a color image of the polishing tape and to output a signal corresponding to the detected color image, and a controller connected to the color image sensor, the controller being adapted to receive the signal output from the color image sensor and to determine when a color of the color image detected by the color image sensor changes, a change in the color image indicating a polishing end point.
摘要翻译：晶片抛光装置包括在两个导辊之间延伸的研磨带，抛光带的与待抛光晶片的表面接触的第一表面，包括推动垫的抛光头，该推动垫适于将抛光带推向要抛光的晶片的表面，邻近抛光带的彩色图像传感器，彩色图像传感器适于检测研磨带的彩色图像并输出与检测到的彩色图像相对应的信号，以及控制器，连接到所述彩色图像传感器，所述控制器适于接收从彩色图像传感器输出的信号，并且确定由彩色图像传感器检测到的彩色图像的颜色何时改变指示抛光终点的彩色图像的变化。

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