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1. 发明授权

US07185133B2 Data processor 有权
公开(公告)号：US07185133B2
公开(公告)日：2007-02-27
申请号：US11142258
申请日：2005-06-02
申请人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
发明人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
IPC分类号： G06F13/36 , G06F12/00
CPC分类号： G06F13/4036
摘要： A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting the first and second buses. The bus bridge circuit has a first transfer controller, responsive to an access request from the first bus to the second bus, for obtaining a bus right of the second bus, and a second transfer controller, responsive to an access request from the second bus to the first bus, for obtaining a bus right of the first bus. The second bus has a first path connecting the second bus slave module and the first transfer controller and a second path connecting the second bus master module and the second transfer controller.

2. 发明申请

US20070112993A1 Data processor 审中-公开
标题翻译：数据处理器
公开(公告)号：US20070112993A1
公开(公告)日：2007-05-17
申请号：US11651495
申请日：2007-01-10
申请人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
发明人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
IPC分类号： G06F13/36
CPC分类号： G06F13/4036
摘要： A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting the first and second buses. The bus bridge circuit has a first transfer controller, responsive to an access request from the first bus to the second bus, for obtaining a bus right of the second bus, and a second transfer controller, responsive to an access request from the second bus to the first bus, for obtaining a bus right of the first bus. The second bus has a first path connecting the second bus slave module and the first transfer controller and a second path connecting the second bus master module and the second transfer controller.
摘要翻译：数据处理器具有连接到第一总线的第一总线主模块，第一总线从模块和第一总线右仲裁电路，第二总线主模块，第二总线从模块和连接到第二总线的第二总线右仲裁电路，以及连接第一和第二巴士的公交桥电路。总线桥电路具有第一传输控制器，响应于从第一总线到第二总线的访问请求，用于获得第二总线的总线权限，以及第二传输控制器，响应于来自第二总线的访问请求第一辆公共汽车，用于获得第一辆公共汽车的公交车。第二总线具有连接第二总线从属模块和第一传输控制器的第一路径以及连接第二总线主模块和第二传输控制器的第二路径。

3. 发明申请

US20050273538A1 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US20050273538A1
公开(公告)日：2005-12-08
申请号：US11142258
申请日：2005-06-02
申请人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
发明人： Tadashi Teranuma , Hironobu Hasegawa , Kunihiko Nishiyama , Yoshihiko Tsuchihashi
IPC分类号： G06F13/36 , G06F13/00 , G06F13/40 , G06F15/78
CPC分类号： G06F13/4036
摘要： A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting the first and second buses. The bus bridge circuit has a first transfer controller, responsive to an access request from the first bus to the second bus, for obtaining a bus right of the second bus, and a second transfer controller, responsive to an access request from the second bus to the first bus, for obtaining a bus right of the first bus. The second bus has a first path connecting the second bus slave module and the first transfer controller and a second path connecting the second bus master module and the second transfer controller.
摘要翻译：数据处理器具有连接到第一总线的第一总线主模块，第一总线从模块和第一总线右仲裁电路，第二总线主模块，第二总线从模块和连接到第二总线的第二总线右仲裁电路，以及连接第一和第二巴士的公交桥电路。总线桥电路具有第一传输控制器，响应于从第一总线到第二总线的访问请求，用于获得第二总线的总线权限，以及第二传输控制器，响应于来自第二总线的访问请求第一辆公共汽车，用于获得第一辆公共汽车的公交车。第二总线具有连接第二总线从属模块和第一传输控制器的第一路径以及连接第二总线主模块和第二传输控制器的第二路径。

4. 发明授权

US07069423B2 Microcomputer 失效
公开(公告)号：US07069423B2
公开(公告)日：2006-06-27
申请号：US10201402
申请日：2002-07-22
申请人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F9/30
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

5. 发明授权

US06209045B1 Data processor and data processing system 失效
标题翻译：数据处理器和数据处理系统
公开(公告)号：US06209045B1
公开(公告)日：2001-03-27
申请号：US09335693
申请日：1999-06-18
申请人： Hironobu Hasegawa , Hiroyuki Sasaki , Masahiko Uraguchi
发明人： Hironobu Hasegawa , Hiroyuki Sasaki , Masahiko Uraguchi
IPC分类号： G06F1314
CPC分类号： G06F11/3656 , G06F11/3648
摘要： A data processor has a ROM that holds a boot program for causing the CPU to transfer a debug program from a serial interface circuit to a debug-use RAM area. When supplied externally with an SDI boot command, the serial interface circuit outputs an SDI interrupt request signal (SDI_boot) to an interrupt controller. The signal causes the CPU to execute the boot program. Debug operations are varied as per the contents of the downloaded debug program, and data exchanges upon debugging are carried out serially.
摘要翻译：数据处理器具有保存用于使CPU将调试程序从串行接口电路传送到调试用RAM区域的引导程序的ROM。当外部提供SDI启动命令时，串行接口电路向中断控制器输出SDI中断请求信号（SDI_boot）。该信号使CPU执行引导程序。调试操作根据下载的调试程序的内容而变化，并且调试时的数据交换顺序执行。

6. 发明申请

US20080294873A1 Microcomputer 失效
标题翻译：微电脑
公开(公告)号：US20080294873A1
公开(公告)日：2008-11-27
申请号：US12075131
申请日：2008-03-07
申请人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
摘要翻译：内置存储器被分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。因此，CPU核心2可以同时将两个数据值从内置存储器传送到DSP引擎3.此外，第三总线XAB和XDB以及第二总线YAB和YDB也与第一总线IAB和IDB分离成为外部接口并且CPU核心2可以与对第二存储器4和6以及第一存储器5和7的访问并行地访问外部存储器。

7. 发明申请

US20060224859A1 Microcomputer 失效
标题翻译：微电脑
公开(公告)号：US20060224859A1
公开(公告)日：2006-10-05
申请号：US11354622
申请日：2006-02-14
申请人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F9/30
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
摘要翻译：内置存储器被分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。由此，CPU核心2可以将来自内置存储器的两个数据值同时传送到DSP引擎3。此外，第三总线XAB和XDB以及第二总线YAB和YDB也与要外部接口的第一总线IAB和IDB分开，并且CPU核心2可以与访问第二存储器4和6并行地访问外部存储器和第一存储器5和7。

8. 发明授权

US07558944B2 Microcomputer 失效
公开(公告)号：US07558944B2
公开(公告)日：2009-07-07
申请号：US12075131
申请日：2008-03-07
申请人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F15/76 , G06F13/00 , G06F9/26
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

9. 发明授权

US5867726A Microcomputer 失效
公开(公告)号：US5867726A
公开(公告)日：1999-02-02
申请号：US630320
申请日：1996-04-10
申请人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F12/06 , G06F9/30 , G06F9/34 , G06F9/355 , G06F9/38 , G06F12/00 , G06F13/16 , G06F15/76 , G06F15/78
CPC分类号： G06F9/3893 , G06F15/7817 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

10. 发明授权

US06434690B1 Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions and CUP-type instructions 失效
标题翻译：具有DSP和CPU的微处理器和识别DSP类型指令和CPU类型指令之间的解码器
公开(公告)号：US06434690B1
公开(公告)日：2002-08-13
申请号：US09229147
申请日：1999-01-11
申请人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F1576
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and
摘要翻译：内置存储器被分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。因此，CPU核心2可以同时将两个数据值从内置存储器传送到DSP引擎3.此外，第三总线XAB和XDB以及第二总线YAB和YDB也与第一总线IAB和IDB分离成为外部接口并且CPU核心2可以与访问第二存储器4和6以及第一存储器5和

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