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    • 2. 发明授权
    • Multifocal ocular lens
    • 多焦眼镜
    • US06260966B1
    • 2001-07-17
    • US09474740
    • 1999-12-29
    • Tadashi SawanoHiroyuki OhyamaKazuya MiyamuraYuuzi GotouHideaki Kondou
    • Tadashi SawanoHiroyuki OhyamaKazuya MiyamuraYuuzi GotouHideaki Kondou
    • G02C704
    • G02C7/044A61F2/1618G02C7/042G02C7/043G02C7/048G02C2202/04
    • A multifocal ocular lens having a vision correction area which includes a central and outer vision correction region, an intermediate region located between the central and outer regions, and an intermediate-distance vision correction region located radially outwardly of and adjacent to the outer region, and which has an optical axis with which centers of these regions are aligned, the central and outer vision correction regions having respective different first and second optical power values, wherein the optical power of the intermediate region located between the central and outer regions is represented by a combination of two different quadratic curves connected to each other at a point of inflection which corresponds to a desired third optical power between the first and second values, and wherein the intermediate-distance vision correction region located radially outwardly of the outer region includes radially inner and outer varying-power zones, the optical power in the radially inner varying-power zone continuously varying from the second value of the outer vision correction region to a predetermined fourth value which is between the first and second values, while the optical power in the radially outer varying-power zone continuously varying from the fourth value to the second value of the outer region.
    • 一种具有视觉矫正区域的多焦点眼镜片,其包括中央和外部视觉矫正区域,位于中心区域和外部区域之间的中间区域以及位于外部区域的径向外侧和与其相邻的中间距离视力矫正区域,以及 其具有这些区域的中心对准的光轴,中央和外部视觉校正区域具有各自不同的第一和第二光学功率值,其中位于中心区域和外部区域之间的中间区域的光功率由 两个不同的二次曲线的组合在拐点处彼此连接,该点对应于在第一和第二值之间的期望的第三光焦度,并且其中位于外部区域径向外侧的中间距离视力校正区域包括径向内部和 外变功率区,光功率在径向 内部变化功率区域从外部视觉校正区域的第二值连续变化到处于第一和第二值之间的预定第四值,而径向外部变化功率区域中的光功率从第四值连续变化到 外部区域的第二个值。
    • 4. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US08039968B2
    • 2011-10-18
    • US12391359
    • 2009-02-24
    • Hideaki KondouHiromasa Fukazawa
    • Hideaki KondouHiromasa Fukazawa
    • H01L23/48
    • H01L23/585H01L23/522H01L23/5226H01L2924/0002H01L2924/14H01L2924/00
    • A semiconductor integrated circuit device including a dummy via is disclosed. In the semiconductor integrated circuit device, problems such as reduction in the designability and increase in fabrication cost which result from the existence of a dummy wire connected to the dummy via are suppressed. The semiconductor integrated circuit device includes a substrate and three or more wiring layers formed on the substrate. The dummy via connects between a first wiring layer and a second wiring layer. The dummy wire connected to the dummy via exists in the second wiring layer. A protrusion amount of the dummy wire is smaller than a protrusion amount of an intermediate wire included in a stacked via structure.
    • 公开了一种包括虚拟通孔的半导体集成电路装置。 在半导体集成电路器件中,抑制了由连接到虚拟通孔的虚拟线的存在而导致的可设计性降低和制造成本增加等问题。 半导体集成电路器件包括衬底和形成在衬底上的三个或更多个布线层。 虚拟通孔连接在第一布线层和第二布线层之间。 连接到虚拟通孔的虚拟线存在于第二布线层中。 虚拟线的突出量小于叠置的通孔结构中包括的中间线的突出量。
    • 7. 发明申请
    • Semiconductor apparatus
    • 半导体装置
    • US20060103402A1
    • 2006-05-18
    • US11270605
    • 2005-11-10
    • Hideaki Kondou
    • Hideaki Kondou
    • G01R31/02
    • G11C29/1201G01R31/31719G11C29/006G11C29/48G11C2029/1206H01L22/32H01L2924/0002H01L2924/00
    • A semiconductor apparatus according to the present invention comprises a semiconductor wafer, a plurality of semiconductor chips provided on the semiconductor wafer, a dicing lane provided between the adjacent two semiconductor chips and representing a region to be cut off when the semiconductor wafer is cut for each of the semiconductor chips and a plurality of probing pads disposed in a row on the dicing lane, and connecting parts for connecting the respective probing pads to one of the semiconductor chips facing each other with the probing pads interposed therebetween, wherein the semiconductor chips are connected to at least one of the plurality of probing pads via the connecting parts.
    • 根据本发明的半导体装置包括半导体晶片,设置在半导体晶片上的多个半导体芯片,设置在相邻的两个半导体芯片之间的切割通道,并且表示当半导体晶片被切割时切割的区域 的半导体芯片和在切割通道上排列成一排的多个探测焊盘,以及连接部分,用于将各个探测焊盘连接到彼此面对的半导体芯片之一,探测焊盘插入其间,其中半导体芯片连接 经由连接部分到达多个探测垫中的至少一个。