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1. 发明授权

US4134076A Pulse width modulated signal amplifier 失效
标题翻译：脉宽调制信号放大器
公开(公告)号：US4134076A
公开(公告)日：1979-01-09
申请号：US857176
申请日：1977-12-02
申请人： Tadao Suzuki , Takeshi Fukami
发明人： Tadao Suzuki , Takeshi Fukami
IPC分类号： H03F3/20 , H03F3/217 , H03F3/38 , H03F3/183
CPC分类号： H03F3/2171 , H03F3/217 , H03F2200/511
摘要： A pulse width modulated signal amplifier includes an integrator having a positive or non-inverted input terminal supplied with a modulating signal, such as, an audio signal, and an inverted input terminal supplied with a rectangular wave signal as a carrier, a high gain amplifier receiving the output of the integrator and producing a pulse width modulated signal, a pulse power amplifier receiving the pulse width modulated signal, a low pass filter receiving the output of the pulse power amplifier and producing an amplified demodulated signal corresponding to the original modulating signal and which is supplied to an output terminal, and a negative feedback circuit connected between the output terminal of the pulse power amplifier and the inverted input terminal of the integrator.
摘要翻译：脉宽调制信号放大器包括积分器，该积分器具有被提供有诸如音频信号的调制信号的正或非反相输入端，以及提供有矩形波信号作为载波的反相输入端，高增益放大器接收积分器的输出并产生脉冲宽度调制信号，接收脉宽调制信号的脉冲功率放大器，接收脉冲功率放大器输出的低通滤波器，并产生对应于原始调制信号的放大解调信号;以及连接在脉冲功率放大器的输出端和积分器的反相输入端之间的负反馈电路。

2. 发明授权

US09553067B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09553067B2
公开(公告)日：2017-01-24
申请号：US15029393
申请日：2014-08-04
申请人： Takeshi Fukami
发明人： Takeshi Fukami
IPC分类号： H01L23/48 , H01L23/00
CPC分类号： H01L24/29 , H01L23/3157 , H01L23/562 , H01L24/32 , H01L24/83 , H01L2224/02165 , H01L2224/04026 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/26125 , H01L2224/29013 , H01L2224/29036 , H01L2224/29076 , H01L2224/29111 , H01L2224/32058 , H01L2224/32245 , H01L2224/83007 , H01L2224/83801 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/0483 , H01L2924/07025 , H01L2924/3512 , H01L2924/00 , H01L2924/01047 , H01L2924/01029 , H01L2924/00014
摘要： A semiconductor device includes a semiconductor layer, an electrode layer arranged on the semiconductor layer, a crack starting point layer arranged above the semiconductor layer, and a solder layer being in contact with the electrode layer and the crack starting point layer. A joining force between the solder layer and the crack starting point layer is smaller than a joining force between the solder layer and the electrode layer.
摘要翻译：半导体器件包括半导体层，布置在半导体层上的电极层，布置在半导体层上方的裂纹起点层，以及与电极层和裂纹起点层接触的焊料层。焊料层和裂纹起点层之间的接合力小于焊料层和电极层之间的接合力。

3. 发明授权

US4600941A Scrambling system for audio frequency signals 失效
标题翻译：音频信号加扰系统
公开(公告)号：US4600941A
公开(公告)日：1986-07-15
申请号：US560957
申请日：1983-12-13
申请人： Akira Sakamoto , Toshihiko Waku , Takeshi Fukami , Masakatsu Toyoshima , Michimasa Komatsubara
发明人： Akira Sakamoto , Toshihiko Waku , Takeshi Fukami , Masakatsu Toyoshima , Michimasa Komatsubara
IPC分类号： H04K1/06 , H04N7/167
CPC分类号： H04K1/06
摘要： A scrambling system for an audio frequency signal in which an audio signal is divided into blocks, each block being formed of a plurality of frames, the plurality of frames are rearranged on a timebase in a predetermined order at every block so as to be encoded and the encoded signal is re-arranged on the timebase in an original order so as to be decoded, in which there are provided a first signal processing circuit for inserting a redundant portion into a portion between adjoining frames and timebase-compressing the frames in response to the redundant portions upon encoding, a control signal generating circuit for inserting a control signal other than an audio information into the redundant portions, a control signal detecting circuit for detecting the control signal upon decoding and a second signal processing circuit for removing the redundant portions in synchronism with the detected control signal and timebase-expanding the frames in response to the redundant portions. Therefore, even when the audio signal is transmitted through a system in a transmission path having a timebase fluctuation such as a transmission path of a VTR (video tape recorder) and the like the frequency band region of which is restricted, the signal waveform is not distorted and a noise is not mixed therein so that the scrambling communication having high quality and high reliability can be presented.
摘要翻译：一种用于音频信号的音频信号的加扰系统，其中音频信号被分成多个块，每个块由多个帧形成，所述多个帧在每个块上以预定顺序在时基上重新排列，以被编码; 编码信号以原始顺序重新排列在时基上以被解码，其中提供了第一信号处理电路，用于将冗余部分插入相邻帧之间的部分，并响应于时基而压缩帧编码后的冗余部分，用于将除音频信息之外的控制信号插入到冗余部分中的控制信号生成电路，用于在解码时检测控制信号的控制信号检测电路和用于去除冗余部分中的冗余部分的第二信号处理电路与检测到的控制信号同步并响应于冗余部分对时基进行扩展。因此，即使音频信号通过具有时频波动的传输路径的系统发送，例如VTR（录像机）的传输路径等，其频带区域被限制，信号波形也不会失真并且不混合噪声，从而可以呈现具有高质量和高可靠性的扰频通信。

4. 发明授权

US4876719A Synchronizing system for digital apparatus 失效
标题翻译：数字设备同步系统
公开(公告)号：US4876719A
公开(公告)日：1989-10-24
申请号：US37382
申请日：1987-04-10
申请人： Taro Nakagami , Takeshi Fukami , Toshiro Terauchi
发明人： Taro Nakagami , Takeshi Fukami , Toshiro Terauchi
IPC分类号： H04L7/04 , G11B20/10 , G11B20/12 , G11B27/00 , G11B27/10 , G11B27/30
CPC分类号： G11B27/3027 , G11B20/10 , G11B20/1262 , G11B27/002 , G11B27/10 , G11B20/1211 , G11B20/1217 , G11B20/1251 , G11B2020/10546 , G11B2220/213 , G11B2220/2545 , G11B2220/913
摘要： A synchronizing system for use with a plurality of digital signal reproducers includes a plurality of digital signal reproducers, each having a digital I/O modulator, a digital I/O demodulator and a decoder; a digital signal multiplexer supplied with the output signal from the plurality of digital signal reproducers, and for producing a frame synchronizing signal, a plural channel of digital signals; the digital signal multiplexer including a clock pulse generator, a word synchronizing signal generator, a digital I/O modulator and a digital I/O demodulator. The corresponding digital I/O modulator and digital I/O demodulator are coupled to each other so as to synchronize the plurality of digital signal reproducers.
摘要翻译：一种与多个数字信号再现器一起使用的同步系统包括多个数字信号再现器，每个具有数字I / O调制器，数字I / O解调器和解码器; 提供有来自多个数字信号再现器的输出信号并产生帧同步信号的数字信号多路复用数字信号; 数字信号多路复用器包括时钟脉冲发生器，字同步信号发生器，数字I / O调制器和数字I / O解调器。相应的数字I / O调制器和数字I / O解调器彼此耦合，以便同步多个数字信号再现器。

5. 发明授权

US4598169A System for detecting a marker signal inserted in an information signal 失效
标题翻译：用于检测插入到信息信号中的标记信号的系统
公开(公告)号：US4598169A
公开(公告)日：1986-07-01
申请号：US563979
申请日：1983-12-21
申请人： Michimasa Komatsubara , Takeshi Fukami , Akira Sakamoto , Takehiro Sugita , Toshiya Miyata
发明人： Michimasa Komatsubara , Takeshi Fukami , Akira Sakamoto , Takehiro Sugita , Toshiya Miyata
IPC分类号： H04K1/06 , H04L7/04 , H04L7/08 , H04L9/00
CPC分类号： H04L7/042 , H04K1/06 , H04L7/08
摘要： A system for detecting a marker signal with a predetermined pattern inserted periodically in an information signal comprises a circuit which repetitively generates window signals and successively shifts the window signals in a step-wise fashion during a predetermined interval, a detecting circuit which employs the window signals to detect at least a portion of a marker signal in the information signal when at least the portion of the detected marker signal occurs during one of the window signals, a circuit which determines when the detected marker signal has the predetermined pattern to generate a net marker signal in response thereto, and a circuit responsive to the net marker signal which repetitively generates subsequent unshifted window signals beginning a predetermined time after the detected marker signal.
摘要翻译：用于在信息信号中周期性地插入预定模式的标记信号的检测系统包括重复产生窗口信号的电路，并且在预定间隔期间逐步地依次移动窗口信号，采用窗口信号的检测电路当检测到的标记信号的至少一部分在窗口信号之一期间发生时，检测信息信号中的标记信号的至少一部分，确定检测到的标记信号何时具有预定模式以产生净标记的电路以及响应于净标记信号的电路，其在检测到的标记信号之后开始预定时间开始重复产生后续未移位窗口信号。

6. 发明申请

US20160284660A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160284660A1
公开(公告)日：2016-09-29
申请号：US15029393
申请日：2014-08-04
申请人： Takeshi Fukami
发明人： Takeshi Fukami
IPC分类号： H01L23/00
CPC分类号： H01L24/29 , H01L23/3157 , H01L23/562 , H01L24/32 , H01L24/83 , H01L2224/02165 , H01L2224/04026 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/26125 , H01L2224/29013 , H01L2224/29036 , H01L2224/29076 , H01L2224/29111 , H01L2224/32058 , H01L2224/32245 , H01L2224/83007 , H01L2224/83801 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/0483 , H01L2924/07025 , H01L2924/3512 , H01L2924/00 , H01L2924/01047 , H01L2924/01029 , H01L2924/00014
摘要： A semiconductor device includes a semiconductor layer, an electrode layer arranged on the semiconductor layer, a crack starting point layer arranged above the semiconductor layer, and a solder layer being in contact with the electrode layer and the crack starting point layer. A joining force between the solder layer and the crack starting point layer is smaller than a joining force between the solder layer and the electrode layer.
摘要翻译：半导体器件包括半导体层，布置在半导体层上的电极层，布置在半导体层上方的裂纹起点层，以及与电极层和裂纹起点层接触的焊料层。焊料层和裂纹起点层之间的接合力小于焊料层和电极层之间的接合力。

7. 发明授权

US4787085A Digital signal transmitting system 失效
标题翻译：数字信号发射系统
公开(公告)号：US4787085A
公开(公告)日：1988-11-22
申请号：US55513
申请日：1987-05-29
申请人： Kohichi Suto , Hisayoshi Sugiyama , Akira Sakamoto , Takeshi Fukami , Toshiro Terauchi , Masakatsu Toyoshima
发明人： Kohichi Suto , Hisayoshi Sugiyama , Akira Sakamoto , Takeshi Fukami , Toshiro Terauchi , Masakatsu Toyoshima
IPC分类号： H04J3/22 , H04J3/16 , H04J3/12
CPC分类号： H04J3/1605
摘要： A digital signal transmitting system includes a plurality of digital signal reproducers, each outputting a digital data signal to be time-division multiplexed; a digital signal multiplexer supplied with a frame synchronizing signal, a service bit signal and the output digital signals from the reproducers and for producing a block data signal including the frame synchronizing signal, the service bit signal and a plurality of slot data bits arranged with the digital data signals, each one bit within a multiple-frame, in which the service bit signal is indicative of the transmission mode and the slot data associated with each of the plurality of digital data signals being transmitted.
摘要翻译：数字信号发送系统包括多个数字信号再现器，每个数字信号再现器输出数字数据信号进行时分复用; 提供有帧同步信号的数字信号多路复用器，服务位信号和来自再现器的输出数字信号，并用于产生包括帧同步信号，服务位信号和多个时隙数据位的块数据信号，数字数据信号，多帧内的每一位，其中服务位信号指示传输模式，并且与所述多个数字数据信号中的每一个相关联的时隙数据被发送。

8. 发明授权

US08755185B2 Semiconductor module 有权
标题翻译：半导体模块
公开(公告)号：US08755185B2
公开(公告)日：2014-06-17
申请号：US13515663
申请日：2010-01-08
申请人： Chung-chih Chou , Takeshi Fukami , Yuji Oda
发明人： Chung-chih Chou , Takeshi Fukami , Yuji Oda
IPC分类号： H05K7/20
CPC分类号： H05K7/20927 , H01L23/3735 , H01L23/473 , H01L24/33 , H01L25/071 , H01L25/18 , H01L2224/06181 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48472 , H01L2224/73265 , H01L2924/1305 , H01L2924/13055 , H01L2924/19107 , H02M7/003 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor module includes an upper arm and a lower arm of an inverter circuit. The upper arm has a switching element and a rectifying device and the lower arm has a switching element and a rectifying device. The upper arm and the lower arm are laminated such that the switching elements overlap each other and the rectifying devices overlap each other. Refrigerant flow paths constituting cooling sections respectively extend along both sides in the lamination direction of the switching elements and the rectifying devices and are folded back at the rectifying device lamination section side.
摘要翻译：半导体模块包括逆变器电路的上臂和下臂。上臂具有开关元件和整流装置，下臂具有开关元件和整流装置。上臂和下臂被层叠，使得开关元件彼此重叠并且整流装置彼此重叠。构成冷却部的制冷剂流路分别沿着开关元件和整流装置的层叠方向的两侧分别延伸，并在整流装置层叠部侧折回。

9. 发明授权

US5031181A Error correction processing apparatus 失效
标题翻译：纠错处理装置
公开(公告)号：US5031181A
公开(公告)日：1991-07-09
申请号：US386787
申请日：1989-07-27
申请人： Yoichiro Sako , Shigeru Imura , Takeshi Fukami
发明人： Yoichiro Sako , Shigeru Imura , Takeshi Fukami
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/15
摘要： An error correcting apparatus including a circuit for detecting error correcting modes of incoming digital information, a generator for generating a first set of syndromes for a first error correcting mode when the incoming digital information is detected as the first error correcting mode, a generator for generating a second set of syndromes for a second error correcting mode when the incoming digital information is detected as the second error correcting mode, a generator for generating quasi-syndromes for the second error correcting mode by adding an additional syndrome to the syndromes for the first error correcting mode when the incoming digital information is detected as the first error correcting mode, and an error correction circuit for applying an error correcting process to the incoming digital information based on the generated syndromes for the second error correcting mode in spite of the error correcting modes of the incoming digital information.
摘要翻译：一种误差校正装置，包括用于检测输入数字信息的误差校正模式的电路，当检测到输入数字信息作为第一纠错模式时，产生用于第一纠错模式的第一组校正子的发生器，当输入的数字信息被检测为第二纠错模式时，用于第二纠错模式的第二组综合征;生成器，用于通过向第一错误的校正子添加附加的综合征来产生用于第二纠错模式的准综合征检测输入数字信息作为第一纠错模式时的校正模式;以及纠错电路，用于基于所生成的第二纠错模式的校正子，对输入的数字信息进行纠错处理，尽管存在纠错模式的传入数字信息。

10. 发明授权

US4612627A Digital signal composing circuit for cross-fade signal processing 失效
标题翻译：用于交叉淡入淡出信号处理的数字信号组合电路
公开(公告)号：US4612627A
公开(公告)日：1986-09-16
申请号：US560956
申请日：1983-12-13
申请人： Takehiro Sugita , Akira Sakamoto , Takeshi Fukami , Michimasa Komatsubara , Akira Shimizu
发明人： Takehiro Sugita , Akira Sakamoto , Takeshi Fukami , Michimasa Komatsubara , Akira Shimizu
IPC分类号： H04K1/00 , G06F17/17 , G11B20/10 , G11B27/038 , H04K1/06 , H04L9/34 , G06F7/52
CPC分类号： G11B20/10527 , G11B27/038 , H04K1/06
摘要： A digital signal composing circuit includes a first selector for selecting a plurality of digital data, a second selector for selecting one of the digital data and a feedback signal, a control circuit for controlling the switching of the first and second selectors and an adding circuit for adding outputs of the first and second selectors and supplying the added output to the second selector as the feedback signal wherein the final output is derived from the adding circuit. Thus, without using any multiplier, the signal processing can be widely used in the digital signal processing such as digital volume, cross-fade, fade-in/-out, mixing, linear interpolation and the like.
摘要翻译：数字信号组合电路包括：用于选择多个数字数据的第一选择器，用于选择数字数据和反馈信号之一的第二选择器，用于控制第一和第二选择器的切换的控制电路和用于添加第一选择器和第二选择器的输出，并将添加的输出提供给第二选择器作为反馈信号，其中最终输出从加法电路导出。因此，在不使用任何乘法器的情况下，信号处理可广泛用于诸如数字音量，交叉淡入淡出，淡入/淡出，混合，线性插值等数字信号处理。

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