专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070238228A1 Manufacturing method for thin film transistor 有权
标题翻译：薄膜晶体管的制造方法
公开(公告)号：US20070238228A1
公开(公告)日：2007-10-11
申请号：US11393436
申请日：2006-03-29
申请人： Ta-Jung Su , Chin-Tzu Kao , Chia-Che Hsu
发明人： Ta-Jung Su , Chin-Tzu Kao , Chia-Che Hsu
IPC分类号： H01L21/84
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A manufacturing method for a thin film transistor (TFT) is provided. In the manufactured TFT, after a source structure, a drain structure and a channel structure are formed, a first photoresist layer is not removed and a second photoresist is formed on the first photoresist layer through which a semiconductor structure is formed. Further, n-type amorphous silicon, poly silicon or an organic metallic compound is used in replace of the conventional metal to form the source and drain structures so as to reduce step number of manufacturing for the TFT.
摘要翻译：提供了薄膜晶体管（TFT）的制造方法。在制造的TFT中，在源极结构形成漏极结构和沟道结构之后，不去除第一光致抗蚀剂层，并且在形成半导体结构的第一光致抗蚀剂层上形成第二光致抗蚀剂。此外，使用n型非晶硅，多晶硅或有机金属化合物代替常规金属以形成源极和漏极结构，以便减少TFT的制造步骤数量。

2. 发明授权

US07754509B2 Manufacturing method for thin film transistor 有权
标题翻译：薄膜晶体管的制造方法
公开(公告)号：US07754509B2
公开(公告)日：2010-07-13
申请号：US11393436
申请日：2006-03-29
申请人： Ta-Jung Su , Chin-Tzu Kao , Chia-Che Hsu
发明人： Ta-Jung Su , Chin-Tzu Kao , Chia-Che Hsu
IPC分类号： H01L21/00
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A manufacturing method for a thin film transistor (TFT) is provided. In the manufactured TFT, after a source structure, a drain structure and a channel structure are formed, a first photoresist layer is not removed and a second photoresist is formed on the first photoresist layer through which a semiconductor structure is formed. Further, n-type amorphous silicon, poly silicon or an organic metallic compound is used in replace of the conventional metal to form the source and drain structures so as to reduce step number of manufacturing for the TFT.
摘要翻译：提供了薄膜晶体管（TFT）的制造方法。在制造的TFT中，在源极结构形成漏极结构和沟道结构之后，不去除第一光致抗蚀剂层，并且在形成半导体结构的第一光致抗蚀剂层上形成第二光致抗蚀剂。此外，使用n型非晶硅，多晶硅或有机金属化合物代替常规金属以形成源极和漏极结构，以便减少TFT的制造步骤数量。

3. 发明申请

US20070155180A1 Thin film etching method 审中-公开
标题翻译：薄膜蚀刻法
公开(公告)号：US20070155180A1
公开(公告)日：2007-07-05
申请号：US11325323
申请日：2006-01-05
申请人： Chia-Che Hsu , Yea-Chung Shih , Mien-Jen Cheng , Cheng-Chang Wu , Jui-Chung Chang
发明人： Chia-Che Hsu , Yea-Chung Shih , Mien-Jen Cheng , Cheng-Chang Wu , Jui-Chung Chang
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/32134 , H01L29/4908
摘要： A thin film etching method is provided, which is used for manufacturing semiconductor device or thin film transistor (TFT) array and through which no undercut may be presented or a good after-etching shape may be achieved with respect to a thin film thus etched. The thin film etching method is performed in a two-stage manner by an etchant and between the two stages a photoresist removing process is inserted where another etchant is used. With execution of the photoresist removing process, the thin film may have an increased contact area with the etchant. As such, any undercut or undesired after-etching shape existed in the thin film etched by the prior art may be eliminated or improved.
摘要翻译：提供了一种薄膜蚀刻方法，其用于制造半导体器件或薄膜晶体管（TFT）阵列，并且通过该薄膜蚀刻方法可能不会产生底切，或者相对于如此蚀刻的薄膜可以实现良好的蚀刻后形状。通过蚀刻剂以两级方式进行薄膜蚀刻方法，并且在两个阶段之间插入使用另一蚀刻剂的光致抗蚀剂去除工艺。通过执行光致抗蚀剂去除工艺，薄膜可以具有与蚀刻剂的增加的接触面积。因此，可以消除或改进由现有技术蚀刻的薄膜中存在的任何底切或不期望的后蚀刻形状。

4. 发明申请

US20090075443A1 METHOD OF FABRICATING FLASH MEMORY 审中-公开
标题翻译：制作闪速存储器的方法
公开(公告)号：US20090075443A1
公开(公告)日：2009-03-19
申请号：US11963866
申请日：2007-12-24
申请人： Chia-Che Hsu , Rex Young , Pin-Yao Wang
发明人： Chia-Che Hsu , Rex Young , Pin-Yao Wang
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114
摘要： A method of fabricating a flash memory includes providing a substrate with a mask layer thereon, forming pluralities of shallow trenches in the substrate, forming a first oxide layer on the substrate and in the shallow trenches, removing a portion of the first oxide layer above the mask layer, forming a second oxide layer on the mask layer and the first oxide layer, wherein the first and second oxide layers have different etching ratios, removing a portion of the second oxide layer positioned above the mask layer so that an STI is formed with the first and the second oxide layers in each shallow trench, removing the mask layer to form recess portions between adjacent STIs, and filling the recess portions with a conductive layer to form floating gates in the recess portions.
摘要翻译：制造闪速存储器的方法包括在其上提供掩模层的衬底，在衬底中形成多个浅沟槽，在衬底上和浅沟槽中形成第一氧化物层，在第一氧化物层的上方去除部分第一氧化物层掩模层，在掩模层和第一氧化物层上形成第二氧化物层，其中第一和第二氧化物层具有不同的蚀刻比率，去除位于掩模层上方的第二氧化物层的一部分，使得STI形成有每个浅沟槽中的第一和第二氧化物层，去除掩模层以形成相邻STI之间的凹部，并且用导电层填充凹部，以在凹部中形成浮栅。

5. 外观设计

USD796947S1 Nut 有权
公开(公告)号：USD796947S1
公开(公告)日：2017-09-12
申请号：US29570153
申请日：2016-07-06
申请人： Chia-Che Hsu
设计人： Chia-Che Hsu

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式