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1. 发明专利

JP2006323023A METHOD FOR FORMING MASK PATTERN 审中-公开
公开(公告)号：JP2006323023A
公开(公告)日：2006-11-30
申请号：JP2005144650
申请日：2005-05-17
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP , NUFLARE TECHNOLOGY INC
发明人： HONDA NORIYUKI , TSUNAKAWA KIYOSHI , WATANABE SUSUMU , YASHIMA JUN , ABE TAKAYUKI , SUZUKI JUNICHI
IPC分类号： G03F1/36 , G03F1/68 , G03F7/20 , G06F17/50 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a mask pattern, with which increase in a time period for drawing is suppressed and improvement of accuracy in drawing is possible. SOLUTION: A layout data of the mask pattern is acquired, and a first correction map, in which first dimensional correction amounts are respectively set to a plurality of first small regions formed by partitioning the mask pattern arrangement surface in a grid, is formed based on the arrangement of the mask pattern. A second correction map, in which second dimensional correction amounts are respectively set to a plurality of second small regions partitioned in the same grid shape as that of the plurality of first small regions and displaced relative to the first small regions, is formed based on the arrangement of the mask pattern. Then the mask pattern is corrected based on the first and the second correction maps. COPYRIGHT: (C)2007,JPO&INPIT

2. 发明专利

JP2006337857A Method for manufacturing semiconductor device, and correction program of chip pattern in semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件中芯片图案的校正程序
公开(公告)号：JP2006337857A
公开(公告)日：2006-12-14
申请号：JP2005164541
申请日：2005-06-03
申请人： Nuflare Technology Inc , Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社ニューフレアテクノロジー , 株式会社東芝
发明人： HONDA NORIYUKI , TSUNAKAWA KIYOSHI , WATANABE SUSUMU , YASHIMA JUN , ABE TAKAYUKI , SUZUKI JUNICHI
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , H01L21/027 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which appropriate correction or transformation can be performed for a divided chip pattern. SOLUTION: The method includes steps of: determining a plurality of computation areas A11, A12 adjacent to each other in a region where chip patterns P29, P30 of a semiconductor device are present on a design plane; forming a computation margin area 59 for each computation area A11 outside and adjacent to the computation area so as to expand the computation area A11 to the computation margin area 59; selecting chip patterns P29, P30 disposed even in a portion in the computation area A11 by each computation area A11, A12; correcting the chip patterns P29, P30 selected in the respective computation areas A11, A12; and fabricating a real pattern on a wafer based on the corrected chip patterns P29b, P30b. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以对分割的芯片图案进行适当的校正或变换的半导体器件的制造方法。解决方案：该方法包括以下步骤：在设计平面上存在半导体器件的芯片图案P29，P30的区域中，确定彼此相邻的多个运算区域A11，A12; 形成计算区域A11的计算边界区域59，将计算区域A11扩展到运算区域59; 选择由计算区域A11，A12设置在计算区域A11的一部分中的芯片图案P29，P30; 校正在各个计算区域A11，A12中选择的芯片图案P29，P30; 以及基于校正的芯片图案P29b，P30b在晶片上制造实际图案。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2003287871A Equipment and method for preparing mask data 有权
标题翻译：用于制备掩模数据的设备和方法
公开(公告)号：JP2003287871A
公开(公告)日：2003-10-10
申请号：JP2002090060
申请日：2002-03-27
申请人： Toshiba Corp , 株式会社東芝
发明人： KOBAYASHI SACHIKO , KOTANI TOSHIYA , TANAKA SATOSHI , WATANABE SUSUMU
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , H01L21/027 , H01L21/82 , G03F1/08
CPC分类号： G03F1/36
摘要： PROBLEM TO BE SOLVED: To provide equipment and a method for preparing mask data in which data processing time is reduced by reducing simulation time by preventing a plurality of time multiple simulation with respect to the same region in preparing the mask data in manufacturing a semiconductor.
SOLUTION: The equipment 100 for preparing the mask data comprises: an input device 1; an output device 2; a communication controller 3; a main storage device 4; a design pattern storage device 5; and a CPU 10. The CPU 10 realizes performance by appropriately making use of the following from a ROM: a split means 11; a correction value calculation means 12; a correction diagram preparation means 13; a first computation center point calculation means 14; a first rectangular region preparation means 15; an optical proximity effect range decision means 16a, a second region radius decision means 16b, and a first region radius decision means 16c as a second simulation region preparation means 16; a second computation center point calculation means 17; and a process simulation performance means 18.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供用于制备掩模数据的设备和方法，其中通过在制备制造中的掩模数据时相对于相同区域防止多次时间多次模拟来减少模拟时间来减少数据处理时间半导体。解决方案：用于制备掩模数据的设备100包括：输入设备1; 输出装置2; 通信控制器3; 主存储装置4; 设计图案存储装置5; 和CPU 10.CPU 10通过从ROM适当地使用以下来实现性能：分割装置11; 校正值计算装置12; 校正图准备装置13; 第一计算中心点计算装置14; 第一矩形区域准备装置15; 光学邻近效应范围决定装置16a，第二区域半径判定装置16b和作为第二模拟区域准备装置16的第一区域半径判定装置16c; 第二计算中心点计算装置17; 和过程模拟性能手段18.版权所有（C）2004，JPO

4. 发明专利

JP2002197130A METHOD AND DEVICE FOR PROCESSING DESIGN PATTERN DATA OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2002197130A
公开(公告)日：2002-07-12
申请号：JP2000398670
申请日：2000-12-27
申请人： TOSHIBA CORP
发明人： YANO MITSUHIRO , WATANABE SUSUMU
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , H01L21/82 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To efficiently conduct a graphic arithmetic processing about pattern data such as a system LSI wherein a range obeying a hierarchical restriction and a range not obeying the hierarchical restriction are mixed. SOLUTION: The range not obeying the hierarchical restriction of a design pattern of a semiconductor integrated circuit and the range obeying the hierarchical restriction of a memory part are divided, and each divided range is subjected to either one suitable graphic arithmetic processing of a hierarchical processing or a flat processing. Therefore, the graphic arithmetic processing can be carried out about pattern data such as a system LSI wherein a range obeying the hierarchical restriction and a range not obeying the hierarchical restriction are mixed.

5. 发明专利

JP2000114379A METHOD FOR DESIGNING INTEGRATED CIRCUITS AND APPARATUS FOR DESIGNING INTEGRATED CIRCUITS 失效
公开(公告)号：JP2000114379A
公开(公告)日：2000-04-21
申请号：JP27559698
申请日：1998-09-29
申请人： TOSHIBA CORP
发明人： WATANABE SUSUMU
IPC分类号： H01L21/82 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To realize high efficiency for parallel processing of an LSI design- layout data while maintaining its layered structure with the use of a computer capable of parallel processing of data. SOLUTION: A first composition is constituted of a cell divided from a design-cell specified by a design-cell-data in an integrated-circuit design layout data under a cell-dividing determining criterion and an internal cell comprising the design cell other than those divided, a plurality of unit groups with an approximately equal data volume by combining the internal cell created, and a hierarchical paralell processing which is included in the internal cell for each unit group. and a second composition comprises restoration of a non-repeated array-data region, excluding data-regions having repeated data from among array-data regions comprising array-data in an integrated-circuit design-layout data by combining a plurality of singular array-cells or unit cells.

6. 发明专利

JPH10334134A METHOD AND DEVICE FOR VERIFYING MASK FORMING DATA, AND COMPUTER-READABLE RECORDING MEDIUM STORED WITH PROGRAM FOR VERIFYING MASK FORMING DATA 失效
公开(公告)号：JPH10334134A
公开(公告)日：1998-12-18
申请号：JP14658297
申请日：1997-06-04
申请人： TOSHIBA CORP
发明人： WATANABE SUSUMU
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To shorten a verifying process time and to eliminate the need for a large-capacity storage file for working in a CAD tool which verifies corrected pattern data. SOLUTION: A data conversion part 14 converts pattern data into mask forming data, a unit area extraction part 15 extracts a unit area including a corrected pattern from the mask forming data before and after the conversion, and a logical difference arithmetic part 16 converts only the mask forming data in the extracted unit area into graphic data to perform a logical difference arithmetic process.

7. 发明专利

JPS63316619A FAULTY FACILITY JUDGING SYSTEM 失效
公开(公告)号：JPS63316619A
公开(公告)日：1988-12-23
申请号：JP15121687
申请日：1987-06-19
申请人： TOKYO ELECTRIC POWER CO , TOSHIBA CORP , HITACHI LTD , MITSUBISHI ELECTRIC CORP
发明人： NAGAHAMA MORIYOSHI , KABASAWA HIROSHI , HO MAMORU , WATANABE SUSUMU
IPC分类号： H02J3/00 , H02H7/26
摘要： PURPOSE:To judge a faulty facility with high speed and high reliability, by combining power interruption facility groups adjoining through trips CD and forming power interruption facility groups, then judging a faulty facility for every group. CONSTITUTION:System information prior to occurrence of system fault, system information immediately after occurrence of fault and trip information of circuit breaker are taken in, then rower interruption systems having electrical relation are classified to form power interruption facility groups R1-R6. Power interruption groups R1, R3 and R5, R6 adjoining through a trip CB are classified into one power interruption facility group, while remaining groups R2, R4 are classified into another group. Operational information for main and standby protection relays is edited for every group so as to judge faulty facility for every group.

8. 发明专利

JPS63199421A CHARGED-BEAM LITHOGRAPHY METHOD 失效
公开(公告)号：JPS63199421A
公开(公告)日：1988-08-17
申请号：JP3271887
申请日：1987-02-16
申请人： TOSHIBA CORP
发明人： IKENAGA OSAMU , WATANABE SUSUMU
IPC分类号： H01L21/027 , H01J37/302 , H01J37/317
摘要： PURPOSE:To remove fundamental figures including undersize sides, to reduce the generation of drawing unit figures to be turned to undersize figures and to improve the precision of a drawing pattern by joining and processing the fundamental figure including the undersize side with adjacent another fundamental figure, dividing the joined fundamental figure and forming a new fundamental figure. CONSTITUTION:A fundamental figure in which a pattern to be shaped is divided is divided into drawing unit figures capable of being formed by a beam molding means with two or more of apertures, and a desired pattern is drawn as the assembly of the drawing unit figures. In such a drawing method, the pattern to be formed is partitioned by segments parallel with the X or Y direction passing through the apex of the pattern and fundamental figure groups 77a-77g are shaped, and fundamental figures 53, 54 in which the fundamental figures 77c, 77e containing undersize sides are joined with adjacent other fundamental figures are divided by segments parallel with the Y or X direction opposite to said dividing segments passing through the apices of the figures 53, 54 and novel fundamental figures are shaped when there are undersize sides less than minimum length allowable as one sides of the drawing unit figures in one sides of virtual rectangles circumscribed with each fundamental figure.

9. 发明专利

JP2003195473A METHOD FOR CORRECTING PATTERN AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003195473A
公开(公告)日：2003-07-09
申请号：JP2001398438
申请日：2001-12-27
申请人： TOSHIBA CORP
发明人： KOBAYASHI SACHIKO , KOTANI TOSHIYA , TANAKA SATOSHI , WATANABE SUSUMU , YANO MITSUHIRO
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To correct a design pattern to a shape suited to mask plotting or inspection by simple processing. SOLUTION: In a pattern correcting method to be executed by a computer, 1st correction for sides satisfying a prescribed condition out of sides constituting a designed pattern is performed by calculating correction values obtained considering an optical proximity effect. Then 2nd correction for sides not satisfying the prescribed condition is performed by using the correction value of the side adjacent to the side not satisfying the prescribed condition out of the sides corrected by the 1st correction and the sides corrected by the 1st correction are connected to each other with a segment. COPYRIGHT: (C)2003,JPO

10. 发明专利

JP2003022952A Drawing data generating system, drawing data generating method, drawing data generating program, method for producing reticle and method for fabricating semiconductor device 审中-公开
标题翻译：绘制数据生成系统，绘制数据生成方法，绘制数据生成程序，生产方法和制造半导体器件的方法
公开(公告)号：JP2003022952A
公开(公告)日：2003-01-24
申请号：JP2001206541
申请日：2001-07-06
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE SUSUMU , YANO MITSUHIRO
IPC分类号： G03F1/68 , G03F1/70 , G03F7/20 , H01L21/027 , G03F1/08
CPC分类号： G03F1/00
摘要： PROBLEM TO BE SOLVED: To generate mask drawing data in which the number of master masks to be generated can be minimized.
SOLUTION: The method for generating drawing data comprises a step (S101) for generating chip division information by dividing a chip pattern such that pattern data obtained by enlarging the chip pattern data of a reticle is contained in the drawing area of a master mask, generating chip layout information of the master mask by assigning the division patterns in the chip division information sequentially to the master mask in the ascending order and registering the chip layout information in a master mask chip layout information memory, a step (S102) for generating the chip pattern data of the master mask by dividing each chip according to the chip layout information of the master mask with reference to the chip pattern data of the reticle and registering the chip pattern data of the master mask in a master mask pattern data memory, and a step (S103) for generating master mask drawing data with reference to the chip layout information of the master mask and the chip pattern data of the master mask.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：生成可以使生成的主掩模的数量最小化的掩模绘图数据。解决方案：用于生成绘图数据的方法包括：步骤（S101），用于通过划分芯片模式来产生芯片分割信息，使得通过将掩模版的芯片图案数据放大而获得的图案数据包含在主掩模的绘图区域中，产生通过将芯片划分信息中的划分模式按升序顺序地分配给主掩模，并将芯片布局信息登记在主掩模芯片布局信息存储器中，将主芯片的芯片布局信息分配给主掩模，步骤（S102）通过参照掩模版的芯片图案数据，根据主掩模的芯片布局信息划分每个芯片并将主掩模的芯片图案数据登记在主掩模图案数据存储器中，从而分割主掩模的图案数据，以及步骤（S103），用于参照主掩模的芯片布局信息和芯片图案数据生成主掩模绘制数据主面具。

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