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1. 发明专利

JP2012141298A Internal structure of nuclear reactor 审中-公开
标题翻译：核反应堆内部结构
公开(公告)号：JP2012141298A
公开(公告)日：2012-07-26
申请号：JP2011272379
申请日：2011-12-13
申请人： Toshiba Corp , 株式会社東芝
发明人： IWAKI CHIKAKO , IKEDA TATSUMI , YAMAMOTO TETSUZO , WATANABE KATSUNOBU , ABE SATORU , UCHIDA KEN , SATO HISAKI , OKUDA TAKESHI , ITO KIICHI
IPC分类号： G21C15/02
CPC分类号： G21C15/02 , G21C5/10 , G21C13/02 , Y02E30/32
摘要： PROBLEM TO BE SOLVED: To uniformize primary coolant flowing down in a downcomer in a circumferential direction and provide the uniformly distributed primary coolant to fuel assemblies.SOLUTION: The internal structure of a nuclear reactor comprises: a reactor pressure vessel 1 to which multiple inlet nozzles 4 are connected; a core barrel 3 surrounding a number of fuel assemblies 2; a downcomer 6 formed between the reactor pressure vessel 1 and the core barrel 3; and a radial key 23 which is arranged at a lower part of the downcomer 6 and positions the core barrel 3 and the reactor pressure vessel 1. The radial key 21 includes an inside member provided on a side of the core barrel 3, and an outside member provided on a side of the reactor pressure vessel 1, and a flow path is provided between the outside member and the inside member.
摘要翻译：要解决的问题：使在下降管中沿周向向下流动的一次冷却剂均匀化并且向燃料组件提供均匀分布的一次冷却剂。解决方案：核反应堆的内部结构包括：多个入口喷嘴4连接的反应堆压力容器1; 围绕多个燃料组件2的芯筒3; 形成在反应堆压力容器1和芯筒3之间的降液管6; 以及设置在降液管6的下部并且定位芯筒3和反应堆压力容器1的径向键23.径向键21包括设置在芯筒3的一侧的内部构件和外部设置在反应堆压力容器1的一侧，并且在外部构件和内部构件之间设置有流动路径。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2009302979A Random number generation device 有权
标题翻译：随机数生成装置
公开(公告)号：JP2009302979A
公开(公告)日：2009-12-24
申请号：JP2008156027
申请日：2008-06-13
申请人： Toshiba Corp , 株式会社東芝
发明人： KOBAYASHI SHIGEKI , UCHIDA KEN , FUJITA SHINOBU , TANAMOTO TETSUFUMI
IPC分类号： H03K3/84 , G06F7/58 , G09C1/00
CPC分类号： H01L29/1054 , G06F7/588 , H01L21/823807 , H01L27/088 , H01L29/7843 , H03K3/84
摘要： PROBLEM TO BE SOLVED: To provide a random number generation device for generating a random number at high speed by increasing an average frequency of a random telegraph signal (RTS) of a metal insulator semiconductor (MIS) FET. SOLUTION: The random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first gate electrode provided on the first channel region; and a first insulating film provided between the first channel region and the first gate electrode, wherein the first insulating film includes a trap for capturing and discharging charge and tensile or compression stress is applied, in a gate length direction, to at least any one of the first channel region and the first insulating film. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种通过增加金属绝缘体半导体（MIS）FET的随机电报信号（RTS）的平均频率来高速产生随机数的随机数生成装置。解决方案：随机数生成装置包括：第一源区域; 第一漏区; 设置在所述第一源极区域和所述第一漏极区域之间的第一沟道区域; 设置在所述第一沟道区上的第一栅电极; 以及第一绝缘膜，其设置在所述第一沟道区域和所述第一栅电极之间，其中所述第一绝缘膜包括用于捕获和放电电荷的阱，并且拉伸或压缩应力沿栅极长度方向施加到至少任一个第一沟道区和第一绝缘膜。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009257918A Cooling device for molten corium 审中-公开
标题翻译：用于搪瓷的冷却装置
公开(公告)号：JP2009257918A
公开(公告)日：2009-11-05
申请号：JP2008106994
申请日：2008-04-16
申请人： Toshiba Corp , 株式会社東芝
发明人： SUZUKI YUKA , TAWARA MIKA , UCHIDA KEN , NAKADA KOTARO , IKEDA HIROSHI , HOASHI EIJI , HAMAZAKI RYOICHI
IPC分类号： G21C9/016
CPC分类号： Y02E30/40
摘要： PROBLEM TO BE SOLVED: To provide a cooling device for molten corium having a cooling channel capable of effectively removing heat from a molten corium over a long time. SOLUTION: A cooling device 7 for molten corium includes: a cone-shaped heat resistance material 12 provided on a pedestal floor 18 below a reactor pressure vessel 1; a cooling channel 11 provided on the lower face of the heat resistance material 12; a water supply vessel 10 provided below the center of the heat resistance material 12; a water supply channel provided at the pedestal floor 18 and a pedestal side wall 19; and a water injection pipe 8 for supplying cooled water to the water supply channel 9 from a water tank 5 provided above a pressure suppression pool 4. The cooling channel 11 has one end that forms a vertical opening 11b rising up at a circumference part, and the other end connected to the water supply vessel 10. At least one of the inner surface of the cooling channel 11, the inner surface of the cylindrical vessel 10, and the channel wall of the water supply channel 9 is applied or coated with a friction decreasing agent. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有能够长时间有效地从熔融的金属中除去热量的冷却通道的熔融金属的冷却装置。解决方案：用于熔融金属的冷却装置7包括：设置在反应堆压力容器1下方的基座地板18上的锥形耐热材料12; 设置在耐热材料12的下表面上的冷却通道11; 设置在耐热材料12的中心下方的供水容器10; 设置在基座台18处的供水通道和基座侧壁19; 以及用于从设置在压力抑制池4上方的水箱5向供水通道9供给冷却水的注水管8.冷却通道11的一端形成在周向部分上升的垂直开口11b，另一端连接到供水容器10.冷却通道11的内表面，圆柱形容器10的内表面和供水通道9的通道壁中的至少一个被施加或涂覆有摩擦降剂。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009004519A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009004519A
公开(公告)日：2009-01-08
申请号：JP2007163123
申请日：2007-06-20
申请人： Toshiba Corp , 株式会社東芝
发明人： KOBAYASHI SHIGEKI , UCHIDA KEN
IPC分类号： H01L21/8238 , H01L21/762 , H01L21/768 , H01L23/52 , H01L27/00 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/41 , H01L29/417 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which does not generate the drop of switching speed of a circuit, while utilizing effectively a stress impression by global strain in a semiconductor device equipped with a CMISFET on a substrate.
SOLUTION: The semiconductor device includes a first element region formed in one side of a substrate, a second element region formed in another side of the substrate, and an insulating layer between the first element region and the second element region, of which the specific inductive capacity is lower than 3.9, wherein an n-type MISFET is formed in the first element region, a p-type MISFET is formed in the second element region, the first element region and the second element region are electrically connected by a wire penetrating the insulating layer, the substrate is curved so that the side in which the first element region is formed becomes a convex shape and the side in which the second element region is formed becomes a concave shape.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种不产生电路切换速度下降的半导体器件，同时在衬底上配备有CMISFET的半导体器件中有效利用全局应变的应力印模。解决方案：半导体器件包括形成在衬底的一侧中的第一元件区域，形成在衬底的另一侧的第二元件区域以及第一元件区域和第二元件区域之间的绝缘层，其中电感率小于3.9，其中在第一元件区域中形成n型MISFET，在第二元件区域中形成p型MISFET，第一元件区域和第二元件区域通过穿过绝缘层的线，基板弯曲，使得形成第一元件区域的一侧成为凸形，并且形成第二元件区域的一侧变成凹形。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008217139A Error estimation device and error estimation method 有权
标题翻译：错误估计设备和错误估计方法
公开(公告)号：JP2008217139A
公开(公告)日：2008-09-18
申请号：JP2007050324
申请日：2007-02-28
申请人： Toshiba Corp , 株式会社東芝
发明人： UCHIDA KEN , YAMAMOTO TETSUZO , YAMAZAKI YUKITAKA , TAKIGAWA YUKIO , SHIMIZU TAKESHI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide an error estimation device and an error estimation method, estimating an estimation width of an analysis value in a numerical solution in consideration of a numerical value related error, an error causing an error of an input value such as a boundary condition, and an error causing geometric dimensional tolerance.
SOLUTION: This error estimation device has: a geometric sensitivity calculation means (a procedure A) calculating sensitivity exerted by increase/decrease of a value of the error width and an error factor with a geometric dimension as the error factor on an attention value in the numerical solution of a prescribed phenomenon; an input value sensitivity calculation means (a procedure B) calculating sensitivity exerted by the increase/decrease of the error width and an error factor with the input value as the error factor on the attraction value in the numerical solution of the prescribed phenomenon; a numerical analysis error width acquisition means (a procedure C) acquiring the error width of a numerical analysis error of the prescribed phenomenon as an error factor; and an error estimation means estimating the error of the attraction value by use of at least one of the error factor of the error width acquired in the procedure C and the sensitivity and the error width calculated in the procedure B or the procedure A (S117).
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供误差估计装置和误差估计方法，考虑到数值相关误差估计数值解析中的分析值的估计宽度，导致输入值的误差的误差例如边界条件和导致几何尺寸公差的误差。解决方案：该误差估计装置具有：几何灵敏度计算装置（步骤A），其计算通过误差宽度的值的增加/减小施加的灵敏度和具有几何尺寸的误差因子作为注意的误差因子价值在规定现象的数值解中; 输入值灵敏度计算装置（程序B）计算出误差宽度的增加/减少所产生的灵敏度和误差因子，其中输入值作为误差因子对规定现象的数值解的吸引值; 将规定的现象的数值分析误差的误差宽度作为误差因子的数值分析误差宽度取得单元（步骤C）以及误差估计装置，通过使用在过程C中获得的误差宽度的误差因子和在过程B或过程A中计算的灵敏度和误差宽度中的至少一个来估计吸引值的误差（S117）。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2005101515A Semiconductor switch 审中-公开
标题翻译：半导体开关
公开(公告)号：JP2005101515A
公开(公告)日：2005-04-14
申请号：JP2004135474
申请日：2004-04-30
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUZAWA KAZUYA , UCHIDA KEN
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/417 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To produce a high integration LSI by realizing a CMOS switch with a microstructure.
SOLUTION: A double gate MOSFET comprises: a semiconductor region 34; a gate insulation film 19 touching the semiconductor region 34; a first gate electrode 22 and second gate electrode 20 sandwitching the semiconductor region 34 through the gate insulation film 19; and conductor regions 31 and 32 touching the semiconductor region 34 on the opposite sides of the first gate electrode 22 and the second gate electrode 20. The channel region is formed of a semiconductor, the source/drain region is formed of a metal, a low level voltage is applied to the first gate electrode 22 and a high level voltage is applied to the second gate electrode 20 during on time, whereas a high level voltage is applied to the first gate electrode 22 and a low level voltage is applied to the second gate electrode 20 during off time. A semiconductor switch where the first gate electrode 22 has a work function smaller than that of the semiconductor region 34, and the second gate electrode 20 has a work function larger than that of the semiconductor region 34 is thereby provided.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过实现具有微结构的CMOS开关来制造高集成度LSI。解决方案：双栅极MOSFET包括：半导体区域34; 接触半导体区域34的栅极绝缘膜19; 通过栅极绝缘膜19对半导体区域34进行开关的第一栅极电极22和第二栅极电极20; 以及与第一栅电极22和第二栅电极20的相对侧接触半导体区域34的导体区域31,32。沟道区域由半导体形成，源极/漏极区域由金属形成，低电平电压施加到第一栅电极22，并且在导通时间期间向第二栅电极20施加高电平电压，而向第一栅电极22施加高电平电压，并且向第二栅电极施加低电平电压关闭时间期间的栅电极20。因此提供了半导体开关，其中第一栅电极22具有比半导体区域34的功函数小的功函数，并且由此提供具有大于半导体区域34的功函数的功函数。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2002164532A LOGIC CIRCUIT 失效
公开(公告)号：JP2002164532A
公开(公告)日：2002-06-07
申请号：JP2000357789
申请日：2000-11-24
申请人： TOSHIBA CORP
发明人： UCHIDA KEN , KOGA JUNJI , OBA RYUJI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/66 , H01L29/788 , H01L29/792 , H01L49/00 , H03K19/08 , H03K19/20
摘要： PROBLEM TO BE SOLVED: To provide an LSI which enables reconfigurable computing by which very large yield improvement can be expected by using an element having a low driving voltage and excellent holding characteristics. SOLUTION: A logic device is equipped with first and second elements 106 and 107 each composed of a conductive island 15 having at least two tunnel barriers 101 and 102, a first electrode 1 and a second electrode 2 connected to the conductive island through the tunnel barriers, and a charge storage area 18 arranged opposite to the conductive island 15, and the first electrode 1 of the first element 106 and the first electrode 1 of the second element 107 are connected.

8. 发明专利

JP2001284474A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, ITS MANUFACTURING METHOD AND DATA STORAGE METHOD 失效
公开(公告)号：JP2001284474A
公开(公告)日：2001-10-12
申请号：JP2000094082
申请日：2000-03-30
申请人： TOSHIBA CORP
发明人： MATSUZAWA KAZUYA , UCHIDA KEN
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and an information storage method which can store in nonvolatile manner both fixed information necessary to be stored permanently and semi-fixed information to be stored trough ex post determination in the same memory region. SOLUTION: The information on the factory shipment can be stored by the existence of the one side of the source/drain diffusion layer of EEPROM. The information proper to users can be written even in the cell holding no diffusion layer by injection of the thermal carrier through the Schottky junction, or by FNT through the diffusion layers. The information on the factory shipment can be read out at all times by erasing the floating gate charge. And then the same function can be realized in the case of utilizing the charge capture using Si3N4 as a storage node, or utilizing the polarization of ferroelectric substance.

9. 发明专利

JP2001257352A MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001257352A
公开(公告)日：2001-09-21
申请号：JP2000066291
申请日：2000-03-10
申请人： TOSHIBA CORP
发明人： UCHIDA KEN , KOGA JUNJI , OBA RYUJI , CHOKAI AKIRA
IPC分类号： H01L27/10 , H01L21/336 , H01L29/66 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device, having a single electronic element which operates stably, even at normal temperature or thereabout. SOLUTION: The method has a process for making a region, which becomes the channel of a single-crystal silicon layer of a semiconductor substrate where the single-crystal silicon layer is formed in a surface thereof thinner than other regions, a process for introducing vacant lattice defects into the single-crystal silicon layer and a process for etching the surface of the single-crystal silicon layer chemically.

10. 发明专利

JP2001007229A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001007229A
公开(公告)日：2001-01-12
申请号：JP17921799
申请日：1999-06-25
申请人： TOSHIBA CORP
发明人： UCHIDA KEN , CHOKAI AKIRA , MATSUZAWA KAZUYA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of obtaining a high implantation efficiency of electrons into a floating gate electrode without employing a complicated element structure. SOLUTION: This semiconductor device is provided with a channel region 4 formed on a semiconductor substrate 1, a first insulating film 5 formed on the channel region 4, a floating gate electrode 6 formed on the first insulating film 5, a second insulating film 7 formed on the floating gate electrode 6, a control gate electrode 8 formed on the second insulating film 7 and a pair of conductive regions 101, 102 interposing the channel region 4 therebetween. At least one of the pair of the conductor regions 101, 102 has a Schottky junction with the channel region 4.

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