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1. 发明专利

JPH07263463A MANUFACTURE OF SCHOTTKY GATE TYPE FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPH07263463A
公开(公告)日：1995-10-13
申请号：JP5429094
申请日：1994-03-25
申请人： TOSHIBA CORP
发明人： MATSUNAGA NORIHIKO , NISHIBORI KAZUYA , KITAURA YOSHIAKI
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE:To provide a manufacturing method of an MESFET wherein gate withstand voltage is improved without decreasing current driving capability, by using a simple method. CONSTITUTION:A gate electrode 3 is formed on a semi-insulating substrate 1 on which an operating layer 2 is formed. By implanting ions, using the gate electrode 3 as a mask, an intermediate concentration layer 5 and a side wall 6 are formed. A high concentration layer 7 for a source and a high concentration layer 8 for a drain are formed by using the side wall 6 as a mask. An insulating film 9 for a spacer is formed by annealing, in order to perform ohmic formation. When resist 4'' is patterned and an ohmic electrode is formed by lift-off, the oxide film 9 for a spacer is etched as far as the gate electrode 3, and an ohmic electrode is formed by lift-off.

2. 发明专利

JPH05218098A HETEROJUNCTION FIELD-EFFECT TRANSISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH05218098A
公开(公告)日：1993-08-27
申请号：JP2112292
申请日：1992-02-06
申请人： TOSHIBA CORP
发明人： TERADA TOSHIYUKI , NAGAOKA MASAMI , INOUE TOMOTOSHI , NISHIBORI KAZUYA , MORITSUKA MAYUMI , MATSUNAGA NORIHIKO
IPC分类号： H01L29/812 , H01L21/338 , H01L29/778
摘要： PURPOSE:To provide a heterojunction field-effect transistor for which the reduction of the source and drain series resistance is implemented. CONSTITUTION:On a semi-insulating GaAs substrate 1, an n-type GaAs operation layer 3 is formed through an i-type GaAs buffer layer 2. A gate electrode 5 is formed on it through an i-type AlGaAs layer 4. The i-type AlGaAs layer 4 is provided immediately below the gate electrode 5. In the source and drain regions, there are provided the n type GaAs layers 61 and 62 which are formed on the n-type GaAs operation layer 3 close to the gate electrode 5, and the n type GaAs layers 71 and 72 which are superposed on them and formed slightly away from the gate region.

3. 发明专利

JPH01251666A MANUFACTURE OF COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPH01251666A
公开(公告)日：1989-10-06
申请号：JP7608188
申请日：1988-03-31
申请人： TOSHIBA CORP
发明人： NAGAOKA MASAMI , NISHIBORI KAZUYA
IPC分类号： H01L29/812 , H01L21/265 , H01L21/324 , H01L21/338 , H01L29/80
摘要： PURPOSE:To manufacture a compound semiconductor field effect transistor of good stability, reproducibility and applicability by coating an upper surface of a gate electrode with a first thin film consisting of an oxide and by conducting heat treatment while coating a surface of a compound semiconductor with a second thin film consisting of a nitride. CONSTITUTION:An n-type GaAs layer 2 is formed by epitaxial growth on a semiinsulating GaAs substrate 1. A tungsten film 3 is deposited by a spattering vaporization method and an SiO2 film 4 is deposited as a first thin film. A mask 42 is provided by patterning SiO241, and a gate electrode 32 is formed by etching a W film 3 therefrom. Then Si ions are implanted into a surface of the substrate 1. As a second thin film, an aluminum nitride film 5, e.g., is deposited on both sides of the substrate 1 by a spattering vaporization method, heat treatment is conducted at a nitrogen atmosphere, and source drain regions 5, 7 are formed. After an AlN film 5 and the mask film 42 are eliminated respectively, source drain electrodes 8, 9 are formed.

4. 发明专利

JPS6386426A MANUFACTURE OF COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6386426A
公开(公告)日：1988-04-16
申请号：JP22973786
申请日：1986-09-30
申请人： TOSHIBA CORP
发明人： NISHIBORI KAZUYA
IPC分类号： H01L21/324 , H01L21/265 , H01L21/316 , H01L21/318 , H01L21/338 , H01L29/80 , H01L29/812
摘要： PURPOSE:To reduce stress and to suppress the external diffusion of Ga and As from a GaAs substrate by a method wherein a laminated film, on which a PSG or BPSG film is deposited on the lower layer as a protective film and a plasma Si3N4 film is deposited on the upper layer, is used on the title semiconductor device. CONSTITUTION:An ion-implanted layer 12 is formed on a semiinsulating GaAs substrate 11 by implanting Si ions. Then, a BPSG film 13 of 1000Angstrom or less in thickness is deposited by performing a CVD method. The concentration of B and the concentration of P of the BPSG film is set at 6% and 7% respectively, and the condition wherein a reflowing will be started at 700 deg.C is used. Then, after a plasma Si3N4 film 14 has been deposited, a heat treatment is performed in an N2 atmosphere. d.

5. 发明专利

JPS62206886A MANUFACTURE OF COMPOUND-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR 失效
公开(公告)号：JPS62206886A
公开(公告)日：1987-09-11
申请号：JP4865686
申请日：1986-03-07
申请人： TOSHIBA CORP
发明人： NAGAOKA MASAMI , KITAURA YOSHIAKI , NISHIBORI KAZUYA
IPC分类号： H01L29/812 , H01L21/265 , H01L21/324 , H01L21/338 , H01L29/80
摘要： PURPOSE:To obtain an excellent Schottky junction easily while improving uniformity and reproducibility by dividing a heat treatment process into at least two steps on manufacture and making the temperature of heat treatment for a gate electrode material lower than a temperature for forming source and drain regions. CONSTITUTION:PSG films 16 are shaped on both surfaces of a substrate 11 through a CVD method or the like, and a crystallized WN film 13b is formed through first heat treatment at a comparatively low temperature. The WN film is crystallized at the low temperature, and hardly diffuses mutually and reacts on the interface with the substrate 11, and the impurity distribution of an N-type active layer 12 hardly alters, also. Si ions are implanted to the whole surface of the substrate 11, PSG films 17 are shaped on both surfaces of the substrate 11, and source and drain regions 14, 15 are formed through second heat treatment at a comparatively high temperature. Since the WN film is thermally treated, crystallized and brought into a stable state previously at the low temperature at that time, it hardly diffuses mutually and reacts between the WN film and the substrate 11 through heat treatment at the high temperature.

6. 发明专利

JP2012119612A Method for measuring impurity concentration profile, wafer for use in the method, and method of manufacturing semiconductor device using the method 审中-公开
标题翻译：用于测量浓度浓度分布的方法，用于该方法的波形的方法和使用该方法制造半导体器件的方法
公开(公告)号：JP2012119612A
公开(公告)日：2012-06-21
申请号：JP2010270218
申请日：2010-12-03
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIBORI KAZUYA
IPC分类号： H01L21/66 , H01L21/331 , H01L29/737
CPC分类号： H01L22/12 , H01L21/02532 , H01L21/02579 , H01L21/0262
摘要： PROBLEM TO BE SOLVED: To provide a method for measuring an impurity concentration profile which allows for accurate control of the impurity concentration and profile of a semiconductor layer, and to provide a wafer for use in the method, and a method of manufacturing a semiconductor device using it.SOLUTION: A wafer to be used comprises a substrate 10, and semiconductor layers 12, 17 provided on the main surface of the substrate 10 and having a first part formed in a plurality of first regions 17a, 17b having areas different from each other on the main surface, and a second part formed in a second region 17c surrounding the first regions 17a, 17b on the main surface and having a structure different from that of the first part. An impurity concentration profile is measured in the depth direction from the surface of a plurality of first parts, and change of the impurity concentration profile dependent on the area of the first part is determined.
摘要翻译：要解决的问题：提供一种用于测量允许精确控制半导体层的杂质浓度和轮廓的杂质浓度分布的方法，并提供用于该方法的晶片及其制造方法使用它的半导体器件。解决方案：所用的晶片包括基板10和设置在基板10的主表面上的半导体层12,17，并且具有形成在多个第一区域17a，17b中的第一部分，该第一部分具有不同于每个的区域另一个在主表面上，第二部分形成在围绕主表面上的第一区域17a，17b的第二区域17c中，并且具有与第一部分不同的结构。从多个第一部分的表面在深度方向上测量杂质浓度分布，并且确定取决于第一部分的面积的杂质浓度分布的变化。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JPH11150124A FIELD EFFECT TRANSISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH11150124A
公开(公告)日：1999-06-02
申请号：JP3005898
申请日：1998-02-12
申请人： TOSHIBA CORP
发明人： YOSHIMURA MISAO , NISHIBORI KAZUYA , KITAURA YOSHIAKI
IPC分类号： H01L29/812 , H01L21/338
摘要： PROBLEM TO BE SOLVED: To shorten the length of a gate electrode of a field effect transistor without deteriorating IV characteristics of the transistor, by providing a second conductivity impurity region which is formed to cover the boundary of at least either one of a source region and a drain region having a first conductivity type and a semiconductor substrate and not to cross the gate electrode. SOLUTION: In a p-type pocket MESFET, p-type pocket regians 17 and 17 are respectively provided below a source regions 16a and part of a channel layer 12 and below a drain region 16b and another part of the layer 12, and a gate electrode 14 is formed on the channel region 12. In addition, a source electrode 18a and a drain electrode 18b are respectively formed on the source and the drain regions 16a and 16b. Since the pocket regions 17 and 17 are formed apart from the gate electrode 14, the regions 17 do not come close to each other, even when the length of the gate electrode 14 is reduced and, since holes generated by impact ionization are concentrated below the channel layer 12, the occurrence of a phenomenon in which the static characteristic of the MESFET is distorted is eliminated.

8. 发明专利

JPH08274256A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08274256A
公开(公告)日：1996-10-18
申请号：JP247596
申请日：1996-01-10
申请人： TOSHIBA CORP
发明人： NISHIBORI KAZUYA , AOYAMA TOMONORI , KITAURA YOSHIAKI , TANABE YOSHIICHI , SUGURO KYOICHI , ABE KAZUHIDE , KOMATSU SHUICHI , OKUWADA HISAMI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/06 , H01L27/095 , H01L29/92
摘要： PURPOSE: To prevent the deterioration in characteristics caused by the oxidization of a capacitor electrode in a capacitor using an oxide dielectric film. CONSTITUTION: A SiO2 film 12 and the first wiring layer 13 are provided on a GaAs substrate 11 in the above-mentioned order. A capacitor 10 is formed on the first wiring layer 13. The lower electrode 14 of the capacitor 10 has a multilayer structure consisting of a Ti layer/Mo layer/Pt layer in the order from the bottom side. The dielectric film 15 of the capacitor 10 consists of strontium titanate. The upper electrode 16a of the capacitor is multilayer constructed by a WNx layer 21 (120nm)/a W-layer 22 (300nm) in the order from lower side. The surface of the upper electrode 16a, which comes in contact with the dielectric film 15a, is prescribed by a tungsten nitride layer 21.

9. 发明专利

JPH08255873A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08255873A
公开(公告)日：1996-10-01
申请号：JP5688795
申请日：1995-03-16
申请人： TOSHIBA CORP
发明人： SASAKI TADAHIRO , NISHIBORI KAZUYA
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE: To prevent radiation between capacitor electrodes and capacitive coupling with other elements by a structure wherein a first conductor film constituting a capacitor is surrounded by a second conductor film through a dielectric film and a second electrode is used as the ground for a first electrode or a shielding member for other element. CONSTITUTION: A first conductor film 7 is formed on a semiconductor substrate 1 or a dielectric substrate, a second conductor film 4 is then formed thereon through a dielectric film 3 and a third conductor film 2 is formed on the second conductor film through the dielectric film 3. The first electrode of a capacitor is provided using the second conductor film and the second electrode of the capacitor is provided using first, third and second conductor films surrounding the second conductor film. The first, second and third conductor films constituting the second electrode are interconnected through contact holes 5, 6 thus equalizing the potential. The first electrode is surrounded by the second electrode and the first electrode can be shielded from the ground or other element contiguous thereto.

10. 发明专利

JPH07183427A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07183427A
公开(公告)日：1995-07-21
申请号：JP32719593
申请日：1993-12-24
申请人： TOSHIBA CORP
发明人： NISHIBORI KAZUYA
IPC分类号： H01L23/12
摘要： PURPOSE:To reduce thermal resistance without changing high frequency characteristics of a passive element, by mounting a transistor in the region where the semiconductor surface is selectively etched and the chip thickness is locally reduced, and mounting a passive element in the thick part which is not etched. CONSTITUTION:A GaAs chip 1 is bonded and mounted on a mounting board 4 made of alumina by using AuSn solder as mounting material 3. A power transistor 2 us formed in a semiconductor region on the bottom surface of a than part where the central region of the GaAs chip 1 is flatly etched to a depth of 0.4mm from the surface. A passive element 5 is mounted on the surface of a thick part of the GaAs chip 1 which part is not etched and 0.6mm in thickness. Thereby thermal resistance can be reduced without changing high frequency characteristics of the passive element 5.

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