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1. 发明专利

JP2013048294A Electronic component module 有权
标题翻译：电子元件模块
公开(公告)号：JP2013048294A
公开(公告)日：2013-03-07
申请号：JP2012255067
申请日：2012-11-21
申请人： Toshiba Corp , 株式会社東芝 , Toshiba Materials Co Ltd , 東芝マテリアル株式会社
发明人： KATO HIROMASA , NABA TAKAYUKI , NAKAYAMA NORIO
IPC分类号： H01L21/52 , H01L25/07 , H01L25/18 , H05K1/18 , H05K3/34
CPC分类号： H01L35/30 , H01L23/3735 , H01L23/473 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2224/29 , H01L2224/29101 , H01L2224/29124 , H01L2224/29139 , H01L2224/29298 , H01L2224/32225 , H01L2224/48091 , H01L2224/83192 , H01L2224/838 , H01L2224/83805 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01105 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/0133 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2924/19107 , H01L2924/351 , H05K1/0201 , H05K1/18 , H05K3/3463 , H01L2924/00 , H01L2924/01014 , H01L2924/01022 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2924/01039
摘要： PROBLEM TO BE SOLVED: To provide an electronic component module that enhances reliability by suppressing detachment of an electronic component from a circuit substrate in high temperature environment.SOLUTION: An electronic component module 1 comprises: a circuit substrate 2 in which first and second metal plates 5 and 7 are bonded to both surfaces of a ceramic substrate 3; an electronic component 9 that is bonded to the first metal plate 5 via a first wax material layer 8 and is operable at least at 125°C; and a base plate 11 bonded to the second metal plate 7 via a second wax material layer 10. The first wax material layer 8 is made of an Ag-Cu system wax material or an Al system wax material having a melting point that is higher than an operating temperature of the electronic component 9 and is in a range of 575 to 730°C. A ratio of a thickness of the first metal plate 5 to a thickness of the second metal plate 7 is in a range of 50 to 200%.
摘要翻译：解决的问题：提供一种通过抑制电子部件在高温环境下从电路基板脱离而提高可靠性的电子部件模块。电子部件模块1包括：电路基板2，其中第一和第二金属板5和7接合到陶瓷基板3的两个表面; 电子部件9，其通过第一蜡材料层8接合到第一金属板5，并且可操作至少125℃; 以及通过第二蜡材料层10接合到第二金属板7的基板11.第一蜡材料层8由Ag-Cu系蜡材料或Al系蜡材料制成，其熔点高于电子部件9的工作温度为575〜730℃的范围。第一金属板5的厚度与第二金属板7的厚度的比率在50〜200％的范围内。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2006199584A Method for producing ceramic circuit board 审中-公开
标题翻译：生产陶瓷电路板的方法
公开(公告)号：JP2006199584A
公开(公告)日：2006-08-03
申请号：JP2006040322
申请日：2006-02-17
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMORIDA YUTAKA , NAKAYAMA NORIO
IPC分类号： C04B35/111 , H01L23/12 , H01L23/15 , H05K1/03 , H05K3/20 , H05K3/38
摘要： PROBLEM TO BE SOLVED: To provide a method for producing a reliable ceramic circuit board which has high withstand voltage characteristics and excellent resistance to the heat cycle as well as a high bending strength (deflective strength), and which rarely causes fractures or dielectric breakdowns even if a high bending load is applied. SOLUTION: The method for producing the ceramic circuit board 1 is characterized in that a raw material mixture comprising a high purity alumina powder of 99.5-99.9% purity to which a sintering aid of less than 0.5 wt.% and an organic binder are added is molded, an alumina substrate 2 containing alumina (Al 2 O 3 ) of 99.5% or more and having a void rate of 5 vol.% or less is prepared by sintering the molded product at a temperature of 1,200-1,700°C for 10-48 hours at normal atmospheric pressure, and metal circuit boards 3, 4 of a predetermined shape are joined onto the resultant alumina substrate 2. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有高耐压特性和优异的耐热循环性以及高弯曲强度（偏转强度）的可靠的陶瓷电路板的制造方法，很少导致断裂或即使施加高的弯曲载荷，绝缘击穿。＆lt; P＆gt;解决方案：陶瓷电路板1的制造方法的特征在于，包含纯度为99.5-99.9％的高纯度氧化铝粉末的原料混合物，烧结助剂小于0.5重量％，有机粘合剂，制备含有99.5％以上且空隙率为5体积％以下的氧化铝的氧化铝基体2（Al 2 SB 3 O 3，SB 3），其空隙率为5体积％以下通过在正常大气压下在1,200-1,700℃的温度下烧结成型制品10-48小时，并将所形成的金属电路板3,4接合到所得的氧化铝基板2上。（版权所有： C）2006，JPO＆NCIPI

3. 发明专利

JP2005268824A Ceramic circuit substrate 有权
标题翻译：陶瓷电路基板
公开(公告)号：JP2005268824A
公开(公告)日：2005-09-29
申请号：JP2005157913
申请日：2005-05-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMORIDA YUTAKA , NAKAYAMA NORIO , IYOGI YASUSHI , NABA TAKAYUKI
IPC分类号： H01L23/12 , H01L23/36 , H01L23/40
CPC分类号： H01L2224/27013 , H01L2224/32225
摘要： PROBLEM TO BE SOLVED: To provide a high-quality ceramic circuit substrate and to improve its production efficiency by preventing the misregistration of a semiconductor pallet caused due to solder flow at the time of soldering and poor pressure withstanding caused by a solder bridge and by implementing a good solder bonding. SOLUTION: For the manufacture of the ceramic circuit substrate with a metallic circuit plate 2a joined on a ceramic substrate 1, and a semiconductor pallet 3 soldered to the metallic circuit plate, a solder resist layer 7 is formed on an unsoldered part of the semiconductor pallet mounting surface of the metallic circuit plate whereby a thickness is the same as or greater than that of a solder layer, and the thickness of the solder resist layer 7 is set to be 5 to 100 μm. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供高质量的陶瓷电路基板，并且通过防止由于焊接时的焊料流动导致的半导体托盘的重合不良以及焊接桥引起的耐压差而提高其生产效率并通过实现良好的焊接。解决方案：为了制造具有连接在陶瓷基板1上的金属电路板2a和焊接到金属电路板的半导体托盘3的陶瓷电路基板，在未焊接的部分上形成阻焊层7 金属电路板的半导体托盘安装面，其厚度与焊料层的厚度相同或更大，阻焊层7的厚度设定为5〜100μm。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2005101415A Ceramic circuit board and method for manufacturing the same 审中-公开
标题翻译：陶瓷电路板及其制造方法
公开(公告)号：JP2005101415A
公开(公告)日：2005-04-14
申请号：JP2003334939
申请日：2003-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAYAMA NORIO , SHIRAI TAKAO , YAMAGUCHI HARUHIKO
IPC分类号： H05K1/09 , H05K1/02 , H05K1/03
摘要： PROBLEM TO BE SOLVED: To provide a small-size ceramic circuit board provided with both ultrafine dimensionally precise wiring and high current-carrying circuit wiring, wherein a high-power semiconductor element is mounted and circuit layer wiring density is enhanced, and to provide a method for manufacturing the circuit board.
SOLUTION: In the ceramic circuit board 1a wherein a circuit layer is integratedly bonded to at least one of surfaces of a ceramic board 2, the circuit layer is constituted of a first circuit layer 6 comprising a braze material and a second circuit layer 7 comprising a metal circuit board 4 bonded to the surface of the ceramic board 2 with the braze material between.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种设置有超细尺寸精密布线和大电流承载电路布线的小尺寸陶瓷电路板，其中安装了大功率半导体元件并提高了电路层布线密度，并且以提供一种制造电路板的方法。解决方案：在电路层与陶瓷板2的至少一个表面整体结合的陶瓷电路板1a中，电路层由包括钎焊材料的第一电路层6和第二电路层 7包括金属电路板4，金属电路板4与陶瓷板2的表面结合，钎焊材料在其间。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2000277741A THIN-FILM TRANSISTOR AND MANUFACTURE OF THE SAME, AND LIQUID CRYSTAL DISPLAY ELEMENT 失效
公开(公告)号：JP2000277741A
公开(公告)日：2000-10-06
申请号：JP7878799
申请日：1999-03-24
申请人： TOSHIBA CORP
发明人： NAKAYAMA NORIO
IPC分类号： H01L29/786 , G02F1/136 , G02F1/1368
摘要： PROBLEM TO BE SOLVED: To provide a thin-film transistor whose characteristics can be made stable, without being affected by the sidewalls of a semiconductor layer. SOLUTION: This thin-film transistor is provided with a semiconductor layer 200 formed island-like on a transparent insulating substrate 100, a gate insulating film 102 formed on the semiconductor layer 200, and a gate electrode 103 pattern-formed via the gate insulating film 102 on the semiconductor layer 200. In this case, the semiconductor layer 200 is provided with a first conductivity region 104 and a second conductivity region 105 including impurity with a prescribed density and a low concentration region 106 which includes impurity with density lower than the prescribed density or showing an intrinsic state. Then, the low concentration region 106 is formed so as to be self-aligned by the pattern of the gate electrode 103, and at least one of the first conductivity region 104 or the second conductivity region 105 is completely surrounded planarly.

6. 发明专利

JPH10275882A SEMICONDUCTOR PACKAGE 失效
公开(公告)号：JPH10275882A
公开(公告)日：1998-10-13
申请号：JP7814997
申请日：1997-03-28
申请人： TOSHIBA CORP
发明人： MONMA JUN , NAKAYAMA NORIO
IPC分类号： H01L23/28 , H01L23/08 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor package of high reliability, so as not to generate damages such as cut, etc., at a bonding portion between a ceramic package and a mounting board by relaxing thermal stresses concentrating on the bonding portion. SOLUTION: A multiplayer ceramic substrate 2 is overlaid on a resin substrate 10 in a form that ball terminals 5 formed on a major surface of the multilayer ceramic substrate 2 as input/output terminals are inserted into through-holes 11 formed in a resin substrate 10. The ball terminals 5 are electrically connected to ball terminals 13, bonded to the mounting surface of the resin substrate 10 through conductive layers 12 in the through-holes 11, and the ball terminals 13 are connected to a wiring on a mounting board with solder. Optimum selection of thermal expansion coefficient of the resin substrate 10 allows the difference in the thermal expansion coefficients between the multilayer ceramic substrate 2 and the mounting board to be relaxed at the resin substrate 10, thus enabling decrease in thermal stresses concentrating on a bonding portion of each ball terminal.

7. 发明专利

JPH1020332A LIQUID CRYSTAL DISPLAY DEVICE AND ITS PRODUCTION 失效
公开(公告)号：JPH1020332A
公开(公告)日：1998-01-23
申请号：JP17524196
申请日：1996-07-04
申请人： TOSHIBA CORP
发明人： NAKAYAMA NORIO
IPC分类号： G02F1/136 , G02F1/1368
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal display device which minimizes the stages to be added, has stable characteristics and does not induce deterioration in grade, such as crosstalks, in image quality. SOLUTION: The channel regions of an amorphous silicon layer 37 have high resistance as well when a source electrode 34 and a drain electrode 36 are held insulated from each other. A region where first and second gate insulating layers 42, 43 and a gate electrode 44 are laminated in the upper part beyond the end of this amorphous silicon layer 37 is connected with the high resistance to two lowresistance regions 39, 40 electrically connected to the source electrode 34 or the drain electrode 35. The degradation of the insulation characteristic between the source electrode 34 and drain electrode 35 of a thin-film transistor(TFT) 46 itself does not arise and leak currents, etc., are not generated. When the source electrode 34 and the drain electrode 35 are held conducting, the channel regions of the amorphous silicon layer 37 turn to the low resistance but since the characteristic itself of the TFT 46 is conducting, thereby the generation of the leak currents are of no problem.

8. 发明专利

JPH09179140A PRODUCTION OF LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPH09179140A
公开(公告)日：1997-07-11
申请号：JP33691395
申请日：1995-12-25
申请人： TOSHIBA CORP
发明人： NAKAYAMA NORIO
IPC分类号： G02F1/136 , G02F1/1368
摘要： PROBLEM TO BE SOLVED: To provide a process for producing a liquid crystal display device which obviates the occurrence of conduction defect without freshly increasing a patterning stage. SOLUTION: Gate lines 3 of aluminum are formed on a glass substrate 1. These gate lines 3 are coated with a gate insulating film 4. A photoresist is patterned and formed on this gate insulating film 4. The gate insulating film 4 is then etched to form openings 16 and thin films 17 of molybdenum are deposited on the gate lines 3 of the openings 16. The photoresist is removed and the thin films 17 are made to remain only in the openings 16 of the gate insulating film 4. Pad electrodes 18 are formed together with display pixel electrodes 9. A matrix array substrate 22 is thus produced. The gate lines 3 of the aluminum and the pad electrodes 18 of ITO are connected via the thin films 17 of the molybdenum and, therefore, the conduction defects are eliminated.

9. 发明专利

JPH01245566A DIODE FOR DETECTING INFRARED RAY 失效
公开(公告)号：JPH01245566A
公开(公告)日：1989-09-29
申请号：JP7189588
申请日：1988-03-28
申请人： TOSHIBA CORP
发明人： NARUSE YUJIRO , SHIGENAKA KEITARO , NAKAYAMA NORIO
IPC分类号： G01J1/02 , H01L31/0264 , H01L31/103
摘要： PURPOSE:To obtain a high infrared ray detecting efficiency by a method wherein the title diode is provided with a semiconductor substrate for transmitting infrared rays, an epitaxially grown layer formed on this semiconductor substrate in such a way that the carrier density in the thickness direction of the layer becomes high at its central part and becomes low on both sides of the density and a signal electrode and an earth electrode, which are formed on this epitaxially grown layer. CONSTITUTION:A signal electrode 4 and an earth electrode 5 are formed on a CMT layer 1 formed on a semiconductor substrate 6. Moreover, in case the P-type CdHgTe (CMT) epitaxially grown layer 1 is continuously formed on the substrate 6, the layer 1 is formed in such a way that the carrier density in the thickness direction of the carrier density layer becomes high at its central part and becomes low on both sides of the carrier density. As this result, in the layer 1, an action to diffuse minority carriers formed by absorption of incident infrared rays in a P-N junction region at a high ratio is generated at the low-carrier density connecting region with the substrate 6, the formation of an ohmic earth electrode is suited at the high carrier density intermediate region and moreover, the formation of an n-type region 11, which is performed by an ion-implantation, is facilitated at the low-carrier density region in the vicinity of the surface. Thereby, a high infrared ray detecting efficiency is obtained.

10. 发明专利

JP2013055264A Manufacturing method of ceramic copper circuit board 审中-公开
标题翻译：陶瓷电路板的制造方法
公开(公告)号：JP2013055264A
公开(公告)日：2013-03-21
申请号：JP2011193400
申请日：2011-09-05
申请人： Toshiba Corp , 株式会社東芝 , Toshiba Materials Co Ltd , 東芝マテリアル株式会社
发明人： HOSHINO MASANORI , SATO HIDEKI , KOMORIDA YUTAKA , NAKAYAMA NORIO , NABA TAKAYUKI
IPC分类号： H05K3/06 , H05K1/03 , H05K3/26
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a ceramic circuit substrate with a reduced etching residue.SOLUTION: The manufacturing method of a ceramic copper circuit substrate has a step of recleaning with acid and alkali after an etching in a method of forming a circuit by etching a copper circuit plate of a predetermined shape on a ceramic circuit substrate bonded with the copper circuit plate on a ceramic substrate. An acid for the recleaning is preferably an oxalic acid solution of 5 wt.% or lower. The ceramic substrate is preferably an alumina substrate.

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