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    • 4. 发明专利
    • DE2853560A1
    • 1979-06-13
    • DE2853560
    • 1978-12-12
    • TOKYO SHIBAURA ELECTRIC CO
    • SHIBAYAMA SHIGEKIIWATA KAZUHIDEOKUDA NOBUO
    • G01N23/04A61B6/03G06F17/17G06T1/00G06T11/00G06F7/38G06F15/42A61B6/00
    • Apparatus for calculating a plurality of interpolation values is adapted to calculate linear interpolation values, consisting of a second data train, from a first data train and includes a memory for storing the first data train and a calculator for calculating the interpolation value from the corresponding two data in the first data train read out of the memory. The calculator comprises an n-bit register for designating those addresses of the memory where data to be read out of the upper m-bit section of the n-bit register is stored and for determining weighted factor data for calculating the interpolation value at the lower (n-m) bit section of the register, a calculating unit for calculating the interpolation value from the data read out of the memory and the weighting coefficient data, an adder for adding a position increment value for designating the adjacent interpolation value to the register each time each interpolation value is calculated at the calculating unit, and a counter stepped one count for each calculation of each interpolation value and adapted to send an end signal to a central processing unit when a predetermined number of counts are completed. The memory, register, adder and counter are controlled by the central processing unit.
    • 6. 发明专利
    • ELECTRON BEAM EXPOSURE APPARATUS
    • JPS5577142A
    • 1980-06-10
    • JP15055778
    • 1978-12-07
    • TOKYO SHIBAURA ELECTRIC CO
    • HITAI YUTAKAOKUDA NOBUO
    • H04N1/387H01J37/302H01L21/027
    • PURPOSE:To accomplish control of the moving direction of the table and the erect image and the image by inversion with single circuit action by arranging a memory for storing patterns corresponding to unit regions, a means of reading thereof, a means of supplying thereof to the beam optical system as serial data converted and a gate means. CONSTITUTION:The circuit is provided with a reflesh memory adapted to store 64 words by 4 bits per word and counters 502 and 503 are provided for accessing thereof. The counter 502 handles the line arrangement on the picture as an up/down counter with a capacity of 4 bits while the counter 503 handles the digit operation as an upcounter with a capacity of 2 bits. In addition, a counter 4 is provided to develop the word timing for the memory 501 by dividing the dot unit pulse from the electron beam optical system into four sections and a 4 bit shift register 506 converts the 4 bit parallel data to the series one to make a data for the optical system 505. Furthermore, the exclusive ''or'' is obtained at the gate 507 to prepare the commands for the moving direction of the table, the reverse reading and the like.
    • 7. 发明专利
    • PATTERN GENERATION SYSTEM
    • JPS5510617A
    • 1980-01-25
    • JP8209678
    • 1978-07-07
    • TOKYO SHIBAURA ELECTRIC CO
    • HITAI YUTAKAOKUDA NOBUO
    • G06K15/10G06F3/153G09G1/00G09G5/24G09G5/36
    • PURPOSE:To eanble an inexpensive display unit ro printer to draw a figure at a high speed. CONSTITUTION:When the coordinates of the 1st terminal point are represented by X1 and Y are those of the 2nd one are by X2 and Y, coordinate data X1, X2 and Y are set in registers 11, 12 and 13. Picture memory 14 has the capacity of four by thirty-two words and each eight-bit word can be assigned by binary seven-bit address information. On receiving coordinate data in registers 11, 12 and 13, address converter circuit 15 calculates address N1 of the word including the 1st terminal point and address N2 of the word including the 2nd terminal point. Obtained address N1 is set in counter 16, and address N2 is in register 17 respectively. Pattern generators 18 and 19 generate eight-bit dot patterns and logic circuit 20 which outputs a dot pattern obtained through bit-by-bit AND operation between the generated dot patterns and register 21 which holds a hot pattern with eight bits all ''1'' are provided. Then, those output dot patterns are supplied to selector circuit 22.