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1. 发明申请

WO2022225940A1 METHOD OF FORMING A FINFET STRUCTURE 审中-公开
公开(公告)号：WO2022225940A1
公开(公告)日：2022-10-27
申请号：PCT/US2022/025363
申请日：2022-04-19
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： HAN, Yun , RANJAN, Alok , VENTZEK, Peter , METZ, Andrew , NIIMI, Hiroaki
IPC分类号： H01L29/66
摘要： A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

2. 发明申请

WO2022125781A1 NON-ATOMIC LAYER DEPOSITION (ALD) METHOD OF FORMING SIDEWALL PASSIVATION LAYER DURING HIGH ASPECT RATIO CARBON LAYER ETCH 审中-公开
公开(公告)号：WO2022125781A1
公开(公告)日：2022-06-16
申请号：PCT/US2021/062620
申请日：2021-12-09
申请人： TOKYO ELECTRON LIMITED [JP]/[JP] , TOKYO ELECTRON U.S. HOLDINGS, INC. [US]/[US]
发明人： CHANG, Shihsheng , O'MEARA, David , METZ, Andrew , HAN, Yun
IPC分类号： H01L21/3065 , H01J37/305 , H01J37/32 , H01L21/02 , H01L21/033
摘要： Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.

3. 发明申请

WO2022256558A1 CYCLIC PLASMA PROCESSING 审中-公开
公开(公告)号：WO2022256558A1
公开(公告)日：2022-12-08
申请号：PCT/US2022/032005
申请日：2022-06-02
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： HAN, Yun , PHILIPPI, Caitlin , METZ, Andrew , RANJAN, Alok
IPC分类号： H01L21/768 , H01L21/311 , H01J37/32
摘要： A method for processing a substrate includes performing a cyclic plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymeric film over the first layer relative to the second layer; purging the plasma processing chamber with an etch gas including fluorine; and exposing the substrate to a second plasma generated from the etch gas to etch the second layer.

4. 发明申请

WO2022256098A1 SACRIFICIAL CAPPING LAYER FOR CONTACT ETCH 审中-公开
公开(公告)号：WO2022256098A1
公开(公告)日：2022-12-08
申请号：PCT/US2022/026455
申请日：2022-04-27
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： HAN, Yun , METZ, Andrew , BIOLSI, Peter
IPC分类号： H01L21/8234 , H01L21/311 , H01L21/768 , H01L21/02
摘要： A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.

5. 发明申请

WO2021221862A1 SYSTEMS AND METHODS TO CONTROL CRITICAL DIMENSION (CD) SHRINK RATIO THROUGH RADIO FREQUENCY (RF) PULSING 审中-公开
公开(公告)号：WO2021221862A1
公开(公告)日：2021-11-04
申请号：PCT/US2021/025912
申请日：2021-04-06
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： SUN, Junling , METZ, Andrew , RALEY, Angelique
IPC分类号： H01L21/311 , H01J37/32 , H01J2237/332 , H01J2237/334 , H01J37/32146 , H01J37/32174 , H01L21/31116 , H01L21/31138
摘要： Systems and methods are provided herein for etch features on a substrate, while maintaining a near-unity critical dimension (CD) shrink ratio. The features etched may include, but are not limited to contacts, vias, etc. More specifically, the techniques described herein use a pulsed plasma to control the polymer build-up ratio between the major CD and minor CD of the feature, and thus, control the CD shrink ratio when etching features having substantially different major and minor dimensions. The CD shrink ratio is controlled by selecting or adjusting one or more operational parameters (e.g., duty cycle, RF power, etch chemistry, etc.) of the plasma etch process(es) to control the amount of polymer build-up at the major and minor dimensions of the feature.

6. 发明申请

WO2020033405A1 METHOD UTILIZING USING POST ETCH PATTERN ENCAPSULATION 审中-公开
公开(公告)号：WO2020033405A1
公开(公告)日：2020-02-13
申请号：PCT/US2019/045304
申请日：2019-08-06
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： RALEY, Angelique , METZ, Andrew , WAJDA, Cory , SUN, Junling
IPC分类号： H01L21/027 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L21/02 , H01L21/56
摘要： A process is provided in which etched layer(s) are protected from residues or defects caused by or resulting from exposure to atmospheric conditions. Protection is provided through the formation of an encapsulation layer post etch. In one embodiment, the encapsulation is provided by a thin layer formed in an atomic layer deposition (ALD) process. The thin layer prevents the etched layer(s) from exposure to air. This encapsulation process may take place after the etch process thus allowing for substrates to be subsequently exposed to atmospheric conditions with little or no queue time constraints being needed for staging subsequent wet clean processing steps. In one embodiment, the encapsulation process may be performed with no vacuum break between the etch process and the encapsulation process. In one embodiment, the encapsulation film is compatible with subsequent wet process steps and can be removed during this wet process steps without adverse effects.

7. 发明申请

WO2022245461A1 CYCLIC PLASMA ETCHING OF CARBON-CONTAINING MATERIALS 审中-公开
公开(公告)号：WO2022245461A1
公开(公告)日：2022-11-24
申请号：PCT/US2022/025534
申请日：2022-04-20
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： KIM, Yunho , ZHANG, Du , CHANG, Shihsheng , WANG, Mingmei , METZ, Andrew
IPC分类号： H01L21/033 , H01L21/311 , H01L21/3213
摘要： A method for processing a substrate includes performing a cyclic process including a plurality of cycles, where the cyclic process includes: forming, in a plasma processing chamber, a passivation layer over sidewalls of a recess in a carbon-containing layer, by exposing the substrate to a first gas including boron, silicon, or aluminum, the carbon-containing layer being disposed over a substrate, purging the plasma processing chamber with a second gas including a hydrogen-containing gas, an oxygen-containing gas, or molecular nitrogen, and exposing the substrate to a plasma generated from the second gas, where each cycle of the plurality of cycles extends the recess vertically into the carbon-containing layer.

8. 发明申请

WO2022177828A1 METHODS FOR FORMING SELF-ALIGNED CONTACTS USING SPIN-ON SILICON CARBIDE 审中-公开
公开(公告)号：WO2022177828A1
公开(公告)日：2022-08-25
申请号：PCT/US2022/016189
申请日：2022-02-11
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： SUN, Junling , HULI, Lior , METZ, Andrew , RALEY, Angelique
IPC分类号： H01L21/8234 , H01L21/768 , H01L21/02
摘要： Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

9. 发明申请

WO2016060864A1 SELF-ALIGNED PATTERNING USING DIRECTED SELF-ASSEMBLY OF BLOCK COPOLYMERS 审中-公开
标题翻译：使用方向自组装块状共聚物的自对准图案
公开(公告)号：WO2016060864A1
公开(公告)日：2016-04-21
申请号：PCT/US2015/053802
申请日：2015-10-02
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： METZ, Andrew , DEVILLIERS, Anton
IPC分类号： H01L21/3065
CPC分类号： H01L21/3086 , H01L21/0271 , H01L21/3081 , H01L21/3088 , H01L21/31133 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： Techniques herein provide methods for self-aligned etching that use existing features for patterning or registering a pattern, without damaging existing features. Existing substrate structures are used to create a surface that enables directed self-assembly (DSA) of block copolymers (BCP) without a separate lithographic patterning layer. Methods herein include recessing at least one existing material or structure on a substrate, and adding a film that remains on the recessed material only. This film can be selected to have a preferential surface energy that enables controlled self-assembly of block copolymers. The substrate can then be etched using both existing structures and one polymer material as an etching mask. One example advantage is that self-assembled polymer material can be located to protect exposed corners of existing features, which reduces a burden of selective etch chemistry, increases precision of subsequent etching, and reduces sputter yield.
摘要翻译：本文提供的技术提供了使用现有特征来图案化或注册图案的自对准蚀刻方法，而不损害现有特征。现有的基板结构用于形成一个能够使嵌段共聚物（BCP）的自组装（DSA）无需单独的光刻图案层的表面。本文的方法包括在衬底上凹陷至少一个现有材料或结构，并且仅添加仅保留在凹陷材料上的膜。该膜可以选择具有能够控制嵌段共聚物自组装的优先表面能。然后可以使用现有结构和一种聚合物材料作为蚀刻掩模来蚀刻衬底。一个示例优点是可以定位自组装的聚合物材料以保护现有特征的暴露角，这减少了选择性蚀刻化学的负担，提高了后续蚀刻的精度，并降低了溅射产率。

10. 发明申请

WO2022226320A1 SACRIFICIAL CAPPING LAYER FOR GATE PROTECTION 审中-公开
公开(公告)号：WO2022226320A1
公开(公告)日：2022-10-27
申请号：PCT/US2022/025969
申请日：2022-04-22
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： HAN, Yun , O'MEARA, David , ALIX, Cheryl , METZ, Andrew , HU, Shan , ZHANG, Henan
IPC分类号： H01L21/8234 , H01L21/768
摘要： A method includes providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate with a dielectric spacer separating each source/drain contact region from adjacent metal gate stacks. Each source/drain region is recessed within an opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the recess and dielectric spacers provide sidewalls. The etch stop layer is formed on the substrate such that it conformally covers the metal gate stacks, the sidewalls and the bottom of each recess, and a sacrificial layer is formed over each of the metal gate stacks and on at least a portion of each sidewall. The etch stop layer is removed from the bottom of each recess to expose the source/drain contact, and the sacrificial layer is then removed from the metal gate stacks and the sidewalls of each recess.

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