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1. 发明申请

WO2011081616A1 A PRIORI PROCESSOR FOR AN ITERATIVE DECODER 审中-公开
标题翻译：一个迭代解码器的优先处理器
公开(公告)号：WO2011081616A1
公开(公告)日：2011-07-07
申请号：PCT/US2009/006723
申请日：2009-12-28
申请人： THOMSON LICENSING , MARKMAN, Ivonete , SHIUE, Dong-chang , GAO, Wen
发明人： MARKMAN, Ivonete , SHIUE, Dong-chang , GAO, Wen
IPC分类号： H03D1/00
CPC分类号： H03M13/3905 , H03M13/3961 , H03M13/6538
摘要： An apparatus for decoding digital data includes a processor to create a priori information for insertion to a maximum a posteriori (MAP) decoder. The processor detects locations of symbols in the input data stream and reads ROM data corresponding to the location. The ROM data is used by the processor to generate a priori information suitable to the input data stream location and inputs the created a priori information into a MAP decoder to aid in the decoding of digital data that is organized in digital symbol blocks of size S, wherein the data stream is encoded by a digital encoder processor comprising a plurality of deterministic digital processing units followed by a trellis encoder.
摘要翻译：用于解码数字数据的装置包括处理器，用于创建用于插入到最大后验（MAP）解码器的先验信息。处理器检测输入数据流中符号的位置，并读取对应于该位置的ROM数据。处理器使用ROM数据来生成适合于输入数据流位置的先验信息，并将所创建的先验信息输入到MAP解码器中，以帮助以大小为S的数字符号块组织的数字数据的解码，其中所述数据流由数字编码器处理器编码，所述数字编码器处理器包括多个确定性数字处理单元，随后是格栅编码器。

2. 发明申请

WO2011046529A1 MAP DECODER ARCHITECTURE FOR A DIGITAL TELEVISION TRELLIS CODE 审中-公开
标题翻译：数字电视机的地图解码器架构代码
公开(公告)号：WO2011046529A1
公开(公告)日：2011-04-21
申请号：PCT/US2009/005577
申请日：2009-10-13
申请人： THOMSON LICENSING , MARKMAN, Ivonete , GAO, Wen
发明人： MARKMAN, Ivonete , GAO, Wen
IPC分类号： H04L5/12
CPC分类号： H04L1/0055 , H04L1/006
摘要： An apparatus for decoding interleaved trellis-encoded digital data includes a metric generator unit that outputs alpha metrics and beta metrics corresponding to each symbol of interleaved trellis-encoded data groups, an alpha unit that inputs the alpha metrics and outputs accumulated alpha state metrics for each trellis encoded data group, a beta unit that inputs the beta metrics and outputs accumulated beta state metrics for each trellis encoded data group, and a log likelihood ratio unit that computes output values corresponding to the digital data using the accumulated alpha state metrics and accumulated beta state metrics. The decoding apparatus incorporates only one set of the metric generator, the alpha unit, the beta unit, and the log likelihood unit to decode information from the plurality of interleaved trellis encoders instead of using a plurality of separate trellis decoders.
摘要翻译：用于解码交织网格编码数字数据的装置包括度量生成单元，其输出与交织网格编码数据组的每个符号相对应的α度量和β度量，输入α度量并输出每个网格编码数据组，输入beta度量并输出每个网格编码数据组的累积beta状态度量的beta单元，以及对数似然比单元，其使用累积的α状态度量和累积的beta来计算与数字数据相对应的输出值状态指标。解码装置仅包含一组度量发生器，α单元，β单元和对数似然单元，以解码来自多个交织网格编码器的信息，而不是使用多个单独的网格解码器。

3. 发明申请

WO2011059419A1 PREAMBLE IDENTIFICATION IN A MOBILE DTV SYSTEM 审中-公开
标题翻译：移动数字电视系统中的前瞻性识别
公开(公告)号：WO2011059419A1
公开(公告)日：2011-05-19
申请号：PCT/US2009/006109
申请日：2009-11-13
申请人： THOMSON LICENSING , MARKMAN, Ivonete , GAO, Wen , CITTA, Richard, W.
发明人： MARKMAN, Ivonete , GAO, Wen , CITTA, Richard, W.
IPC分类号： H04L27/28
CPC分类号： H04L27/02 , H04L1/0041 , H04L25/03171 , H04N21/2383 , H04N21/4382
摘要： A preamble identifier flag in a reserved portion of a data field synchronization segment in a digital television (DTV) data field identifies the presence of preamble training data in a forward error correction (FEC) encoded portion of the DTV data field. The data field synchronization segment is not FEC encoded, thereby allowing detection of the preamble identifier flag without FEC decoding. The detection at a receiver of the preamble identifier flag in a DTV data field allows receiver elements, such as an equalizer and a FEC decoder, to more readily obtain and utilize the preamble training data, thereby enhancing reception and/or simplifying receiver design.
摘要翻译：数字电视（DTV）数据字段中的数据字段同步段的保留部分中的前同步码标识符标识在DTV数据字段的前向纠错（FEC）编码部分中存在前同步码训练数据。数据字段同步段不进行FEC编码，从而允许检测前导码标识符标志而不进行FEC解码。在DTV数据字段中的前导标识符标志的接收机处的检测允许诸如均衡器和FEC解码器之类的接收器元件更容易地获得和利用前导码训练数据，从而增强接收和/或简化接收机设计。

4. 发明申请

WO2011068498A1 DIVERSITY ARCHITECTURE FOR A MOBILE DTV SYSTEM 审中-公开
标题翻译：移动数字电视系统的多样性架构
公开(公告)号：WO2011068498A1
公开(公告)日：2011-06-09
申请号：PCT/US2009/006373
申请日：2009-12-03
申请人： THOMSON LICENSING , MARKMAN, Ivonete , BOUILLET, Aaron Reel
发明人： MARKMAN, Ivonete , BOUILLET, Aaron Reel
IPC分类号： H03M13/00
CPC分类号： H03M13/3707 , H03M13/15 , H03M13/1515 , H03M13/2707 , H03M13/2732 , H03M13/2933 , H03M13/2936 , H03M13/2945 , H03M13/2966
摘要： An apparatus for receiving a digital data stream includes a demodulator that receives a digital data stream including alternating information and parity blocks. The apparatus demodulates the digital stream. An equalizer compensates for distortions in the digital data stream to generate a compensated digital data stream. A delay buffer generates a first stream of digital data representing the compensated digital data stream and a second stream of digital data representing the compensated digital data stream delayed for a predetermined period of time. A forward error correction block receives and processes the first and second streams of digital data from the delay buffer, and outputs an error corrected stream of digital data. A transport block receives and processes the error corrected stream from the forward error correction block for display.
摘要翻译：一种用于接收数字数据流的装置包括一个解调器，其接收包括交替信息和奇偶校验块的数字数据流。该装置解调数字流。均衡器补偿数字数据流中的失真以产生补偿的数字数据流。延迟缓冲器产生表示经补偿的数字数据流的第一数字数据流和表示在预定时间段内延迟的经补偿的数字数据流的第二数字数据流。前向纠错块从延迟缓冲器接收并处理第一和第二数字数据流，并输出纠错的数字数据流。传输块从前向纠错块接收并处理纠错流，以进行显示。

5. 发明申请

WO2005114892A1 CARRIER PHASE AMBIGUITY CORRECTION 审中-公开
标题翻译：载波相位修正
公开(公告)号：WO2005114892A1
公开(公告)日：2005-12-01
申请号：PCT/US2005/010519
申请日：2005-03-29
申请人： THOMSON LICENSING S.A. , MARKMAN, Ivonete , EDDE, Gabriel, Alfred
发明人： MARKMAN, Ivonete , EDDE, Gabriel, Alfred
IPC分类号： H04L7/02
CPC分类号： H04L7/0054
摘要： A receiver comprises a demodulator for providing a demodulated signal and a centroid calculator responsive to the demodulated signal for identifying a correct carrier phase for use in the centroid calculation and in removing carrier phase ambiguity in the demodulator. In addition, the centroid calculator may include a limiter.
摘要翻译：接收机包括用于提供解调信号的解调器和响应于解调信号的质心计算器，用于识别在质心计算中使用的正确载波相位，以及消除解调器中的载波相位模糊度。另外，重心计算器可以包括限制器。

6. 发明申请

WO2003090451A3 HDTV TRELLIS DECODER ARCHITECTURE 审中-公开
公开(公告)号：WO2003090451A3
公开(公告)日：2003-10-30
申请号：PCT/US2003/009862
申请日：2003-04-01
申请人： THOMSON LICENSING S.A. , MARKMAN, Ivonete
发明人： MARKMAN, Ivonete
IPC分类号： H04L5/12
摘要： A trellis decoding system (1) for use in processing a High Definition Television signal. The trellis decoding system includes a traceback unit (33) that identifies a sequence of antecedent trellis states in accordance with a state transition trellis. A branch metric computer (2) includes eight discrete subunits (3), one for each possible trellis state. Each subunit (3) generates two output bits (14, 15) indicative of the two trellis branches exiting the trellis state represente by that particular subunit (3). An add-compare-select unit (8) includes eight discrete subunits (23), each associated with a particular trellis state. Each subunit (23) includes as an input two bits (28, 29) received from the branch metric computer (2) and as an output two bits (6, 31). Bit 31 is chosen from 28 and 29. Bit 6 is chosen from the branch metric information (26, 27) input to each subunit (23). A traceback control and memory unit (33) includes an N to 1 multiplier (49) which receives as an input the output bits (6, 31) from the add-compare-select unit (8). The present system offers a hardware reduction from prior art.

7. 发明申请

WO2003090439A3 CONCATENATED EQUALIZER/TRELLIS DECODER ARCHITECTURE FOR AN HDTV RECEIVER 审中-公开
公开(公告)号：WO2003090439A3
公开(公告)日：2003-10-30
申请号：PCT/US2003/010888
申请日：2003-04-09
申请人： THOMSON LICENSING S.A. , HEO, Seo, Weon , PARK, Jeongsoon , GELFAND, Saul, Brian , MARKMAN, Ivonete
发明人： HEO, Seo, Weon , PARK, Jeongsoon , GELFAND, Saul, Brian , MARKMAN, Ivonete
IPC分类号： H04L27/01
摘要： A concatenated equalizer/trellis decoding system for use in processing a High Definition Television signal. The re-encoded trellis decoder output (6), rather than the equalizer output (19), is used as an input to the feedback filter (8) of the decision feedback equalizer (4). Hard or soft decision trellis decoding may be applied. In order to account for the latency associated with trellis decoding and the presence of twelve interleaved decoders, feedback from the trellis decoder to the equalizer is performed by replicating the trellis decoder and equalizer hardware in a module (1) that can be cascaded in as many stages as needed to achieve the desired balance between complexity and performance. The present system offers an improvement of between 0.6 and 1.9 decibels. Cascading of two modules (1) is usually sufficient to achieve most of the potential performance improvement.

8. 发明申请

WO2003090439A2 CONCATENATED EQUALIZER/TRELLIS DECODER ARCHITECTURE FOR AN HDTV RECEIVER 审中-公开
标题翻译：针对高清晰度电视接收机的定义均衡器/ TRELLIS解码器架构
公开(公告)号：WO2003090439A2
公开(公告)日：2003-10-30
申请号：PCT/US2003/010888
申请日：2003-04-09
申请人： THOMSON LICENSING S.A. , HEO, Seo, Weon , PARK, Jeongsoon , GELFAND, Saul, Brian , MARKMAN, Ivonete
发明人： HEO, Seo, Weon , PARK, Jeongsoon , GELFAND, Saul, Brian , MARKMAN, Ivonete
IPC分类号： H04N
CPC分类号： H04N21/4382 , H03M13/256 , H03M13/3746 , H03M13/6331 , H04L1/0055 , H04L1/006 , H04L1/208 , H04L25/03057 , H04L2025/03382 , H04L2025/0349 , H04L2025/037 , H04L2025/03732 , H04N5/211 , H04N5/4401
摘要： A concatenated equalizer/trellis decoding system for use in processing a High Definition Television signal. The re-encoded trellis decoder output (6), rather than the equalizer output (19), is used as an input to the feedback filter (8) of the decision feedback equalizer (4). Hard or soft decision trellis decoding may be applied. In order to account for the latency associated with trellis decoding and the presence of twelve interleaved decoders, feedback from the trellis decoder to the equalizer is performed by replicating the trellis decoder and equalizer hardware in a module (1) that can be cascaded in as many stages as needed to achieve the desired balance between complexity and performance. The present system offers an improvement of between 0.6 and 1.9 decibels. Cascading of two modules (1) is usually sufficient to achieve most of the potential performance improvement.
摘要翻译：用于处理高分辨率电视信号的级联均衡器/网格解码系统。重新编码的网格解码器输出（6）而不是均衡器输出（19）被用作到判决反馈均衡器（4）的反馈滤波器（8）的输入。可以应用硬或软决策网格解码。为了解决与网格解码相关联的延迟和存在十二个交错解码器，从网格解码器到均衡器的反馈是通过复制模块（1）中的网格解码器和均衡器硬件来实现的，模块（1）可以被级联在尽可能多的根据需要分阶段实现复杂性和性能之间的理想平衡。本系统提供0.6至1.9分贝之间的改进。两个模块（1）的级联通常足以实现大部分潜在的性能改进。

9. 发明公开

EP1495538A1 EQUALIZER MODE SWITCH 有权
标题翻译：均衡器模式开关
公开(公告)号：EP1495538A1
公开(公告)日：2005-01-12
申请号：EP03746961.6
申请日：2003-04-11
申请人： Thomson Licensing S.A. , Markman, Ivonete
发明人： MARKMAN, Ivonete , PARK, Jeongsoon , HEO, Seo, Weon , GELFAND, Saul, Brian
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/037 , H04L2025/03732 , H04N5/211
摘要： An apparatus for automatically selecting one of a standard decision directed (dd) mode and a soft dd mode in a decision feedback equalizer (DFE) for receiving a data signal comprises an equalizer for providing a DFE output signal and having a control input responsive to a control signal exhibiting a first value for selecting the standard dd mode and a second value for selecting the soft dd mode. The equalizer includes a lock detector (20) having an output for providing a lock signal indicative of equalizer convergence. The apparatus includes a mode selector (18) having an input coupled to the lock detector (20) output and having an output coupled to the control input for providing an output signal exhibiting one of the first and second values depending upon characteristics of the lock signal.

10. 发明申请

WO2011068497A1 RELIABLE DIVERSITY ARCHITECTURE FOR A MOBILE DTV SYSTEM 审中-公开
标题翻译：可移动数字电视系统的可靠多样性架构
公开(公告)号：WO2011068497A1
公开(公告)日：2011-06-09
申请号：PCT/US2009/006369
申请日：2009-12-03
申请人： THOMSON LICENSING , MARKMAN, Ivonete , BOUILLET, Aaron Reel , LOPRESTO, Scott Michael
发明人： MARKMAN, Ivonete , BOUILLET, Aaron Reel , LOPRESTO, Scott Michael
IPC分类号： H04H40/00
CPC分类号： H04H60/11 , H04H40/18 , H04L1/0057
摘要： A digital data stream comprises alternating groups of information blocks and groups of parity blocks, each group of information blocks includes multiple information blocks and each group of parity blocks includes multiple parity blocks. An apparatus for receiving a digital data stream comprises a demodulator that receives and demodulates a digital data stream. An equalizer compensates for distortions in the digital data stream. A delay buffer generates a first stream of digital data representing the compensated digital data stream and a second stream of digital data representing a delayed version of the compensated digital data stream. A forward error correction block receives and processes the first and second streams of digital data from the delay buffer, and outputs an error corrected stream of digital data. A transport block receives and processes the error corrected stream from the forward error correction block for display
摘要翻译：数字数据流包括交替的信息块组和奇偶校验块组，每组信息块包括多个信息块，并且每组奇偶校验块包括多个奇偶校验块。一种用于接收数字数据流的装置包括接收和解调数字数据流的解调器。均衡器补偿数字数据流中的失真。延迟缓冲器产生表示经补偿的数字数据流的第一数字数据流和表示经补偿的数字数据流的延迟版本的第二数字数据流。前向纠错块从延迟缓冲器接收并处理第一和第二数字数据流，并输出纠错的数字数据流。传输块从前向纠错块接收并处理纠错流，以进行显示

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