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1. 发明专利

DE60108636T2 未知
公开(公告)号：DE60108636T2
公开(公告)日：2005-06-23
申请号：DE60108636
申请日：2001-07-06
申请人： THIN FILM ELECTRONICS ASA OSLO
发明人： THOMPSON MICHAEL , NORDAL PER-ERIK , GUSTAFSSON GOERAN , CARLSSON JOHAN , GUDESEN GUDE
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C7/06 , G11C7/10 , G11C8/18 , G11C11/22 , G11C7/00 , G11C8/00
摘要： A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.

2. 发明专利

DE60109307T2 未知
公开(公告)号：DE60109307T2
公开(公告)日：2006-04-13
申请号：DE60109307
申请日：2001-08-24
申请人： THIN FILM ELECTRONICS ASA OSLO
发明人： THOMPSON MICHAEL , WOMACK RICHARD , GUSTAFSSON GOERAN , CARLSSON JOHAN
IPC分类号： G11C5/00 , G11C7/06 , G11C7/10 , G11C11/22 , H01L21/8246 , H01L27/105
摘要： In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis, first and second sets (14; 15) of addressing electrodes constitute word lines (WL) and bit lines (BL) of the memory device. A memory cell (13) is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) with each segments sharing and being defined by adjoining bit lines (BL). Means (25) are provided for connecting each bit line (BL) of a segment (S) with a sensing means (26), thus enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL) of the segment (S). Each sensing means (26) senses the charge flow in a bit line (BL) in order to determine a stored logical value. In a readout method a word line (WL) of a segment (S) is activated by setting its potential to a switching voltage Vs of the memory cell (13) during at least a portion of a read cycle, while keeping the bit lines (BL) of the segment (S) at zero potential, during which read cycle a logical value stored in the individual memory cells (13) is sensed by the sensing means (26). -Use in a volumetric data storage apparatus.

3. 发明专利

DE60109307D1 未知
公开(公告)号：DE60109307D1
公开(公告)日：2005-04-14
申请号：DE60109307
申请日：2001-08-24
申请人： THIN FILM ELECTRONICS ASA OSLO
发明人： THOMPSON MICHAEL , WOMACK RICHARD , GUSTAFSSON GOERAN , CARLSSON JOHAN
IPC分类号： G11C7/06 , G11C7/10 , G11C11/22 , H01L21/8246 , H01L27/105 , G11C5/00
摘要： In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis, first and second sets (14; 15) of addressing electrodes constitute word lines (WL) and bit lines (BL) of the memory device. A memory cell (13) is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) with each segments sharing and being defined by adjoining bit lines (BL). Means (25) are provided for connecting each bit line (BL) of a segment (S) with a sensing means (26), thus enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL) of the segment (S). Each sensing means (26) senses the charge flow in a bit line (BL) in order to determine a stored logical value. In a readout method a word line (WL) of a segment (S) is activated by setting its potential to a switching voltage Vs of the memory cell (13) during at least a portion of a read cycle, while keeping the bit lines (BL) of the segment (S) at zero potential, during which read cycle a logical value stored in the individual memory cells (13) is sensed by the sensing means (26). -Use in a volumetric data storage apparatus.

4. 发明专利

DE60108636D1 未知
公开(公告)号：DE60108636D1
公开(公告)日：2005-03-03
申请号：DE60108636
申请日：2001-07-06
申请人： THIN FILM ELECTRONICS ASA OSLO
发明人： THOMPSON MICHAEL , NORDAL PER-ERIK , GUSTAFSSON GOERAN , CARLSSON JOHAN , GUDESEN GUDE
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C7/06 , G11C7/10 , G11C8/18 , G11C11/22 , G11C7/00 , G11C8/00
摘要： A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.

5. 发明专利

DE69902441T2 未知
公开(公告)号：DE69902441T2
公开(公告)日：2003-04-17
申请号：DE69902441
申请日：1999-01-14
申请人： THIN FILM ELECTRONICS ASA OSLO
发明人： BERGGREN MAGNUS , GUSTAFSSON GOERAN , KARLSSON ROGER
IPC分类号： H01L29/772 , H01L21/335 , H01L21/336 , H01L21/337 , H01L21/338 , H01L29/78 , H01L29/786 , H01L29/80 , H01L29/808 , H01L51/10
摘要： A field-effect transistor is made with electrodes (2, 4, 5) and isolators (3) in vertically provided layers, such that at least the electrodes (4, 5) and the isolators (3) form a step (6) oriented vertically relative to the first electrode (2) or the substrate (1). Implemented as a junction field-effect transistor (JFET) or a metal-oxide semiconducting field-effect transistor (MOSFET) the electrodes (2, 5) forming respectively the drain and source electrode of the field-effect transistor or vice versa and the electrode (4) the gate electrode of the field-effect transistor. Over the layers in the vertical step (6) an amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor material is provided and forms the active semiconductor of the transistor contacting the gate electrode (8) directly or indirectly and forming a vertically oriented transistor channel (9) of the p or n type between the first (2) and the second (5) electrode. In a method for fabrication of a field effect transistor a vertical step (6) is formed by a means of a photolithographic process and a soluble amorphous active semiconductor material (8) is deposited over the first electrode (2) and the vertical step (6) such that a vertically oriented transistor channel between the drain and source electrode (2, 5) is obtained. In a JFET the semiconductor material (8) contacts the gate electrode (4) directly. In a MOSFET a vertically oriented gate isolator (7) is provided between the gate electrode (4) and the semiconductor material (8).

6. 发明专利

DE69902441D1 未知
公开(公告)号：DE69902441D1
公开(公告)日：2002-09-12
申请号：DE69902441
申请日：1999-01-14
申请人： THIN FILM ELECTRONICS ASA OSLO
发明人： BERGGREN MAGNUS , GUSTAFSSON GOERAN , KARLSSON ROGER
IPC分类号： H01L29/772 , H01L21/335 , H01L21/336 , H01L21/337 , H01L21/338 , H01L29/78 , H01L29/786 , H01L29/80 , H01L29/808 , H01L51/10
摘要： A field-effect transistor is made with electrodes (2, 4, 5) and isolators (3) in vertically provided layers, such that at least the electrodes (4, 5) and the isolators (3) form a step (6) oriented vertically relative to the first electrode (2) or the substrate (1). Implemented as a junction field-effect transistor (JFET) or a metal-oxide semiconducting field-effect transistor (MOSFET) the electrodes (2, 5) forming respectively the drain and source electrode of the field-effect transistor or vice versa and the electrode (4) the gate electrode of the field-effect transistor. Over the layers in the vertical step (6) an amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor material is provided and forms the active semiconductor of the transistor contacting the gate electrode (8) directly or indirectly and forming a vertically oriented transistor channel (9) of the p or n type between the first (2) and the second (5) electrode. In a method for fabrication of a field effect transistor a vertical step (6) is formed by a means of a photolithographic process and a soluble amorphous active semiconductor material (8) is deposited over the first electrode (2) and the vertical step (6) such that a vertically oriented transistor channel between the drain and source electrode (2, 5) is obtained. In a JFET the semiconductor material (8) contacts the gate electrode (4) directly. In a MOSFET a vertically oriented gate isolator (7) is provided between the gate electrode (4) and the semiconductor material (8).

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