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    • 1. 发明申请
    • ZERO-POWER SAMPLING SAR ADC CIRCUIT AND METHOD
    • 零功率采样SAR ADC电路和方法
    • WO2012151491A3
    • 2013-01-31
    • PCT/US2012036529
    • 2012-05-04
    • TEXAS INSTRUMENTS INCTEXAS INSTRUMENTS JAPANWANG YANKALTHOFF TIMOTHY VWU MICHAEL A
    • WANG YANKALTHOFF TIMOTHY VWU MICHAEL A
    • H03M1/12H03F3/70
    • H03M1/1295H03M1/468
    • A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN + ) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN -) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.
    • 开关电容电路(10,32或32A)通过将求和导体(13)的顶板切换到第一参考电压(VSS)将第一信号(VIN +)取样到第一电容器(C1或CIN1)上, 并将其底板切换到第一信号。 将第二信号(VIN-)通过将其顶板切换到第二信号并将其底板切换到第一参考电压而被采样到第二电容器(C3或CIN3)上。 在采样之后,第二电容器的顶板耦合到第一电容器的顶板。 第二电容器的底板耦合到第一参考电压。 第一电容器的底板耦合到第二参考电压(VDD或VREF),从而从第一导体(13)消除共模输入电压分量的至少一部分,将采样的差分电荷保持在求和 并在其上建立预定的共模电压,并且防止求和导体具有允许从其中泄漏电荷的电压。 开关电容电路可以是SAR,积分器或放大器。