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1. 发明申请

WO2017151827A1 OUTPUT DRIVE WITH POWER DOWN PROTECTION 审中-公开
标题翻译：输出驱动器具有掉电保护功能
公开(公告)号：WO2017151827A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/020294
申请日：2017-03-01
申请人： TEXAS INSTRUMENT INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： WU, Xiaoju , KELOTH, Rajesh , PRASAD, Sudheer
IPC分类号： H01L29/94 , H01L29/772 , H01L21/8224 , H02H7/09
摘要： In described examples, an interface device (300) includes an NPN structure (Ql) along a horizontal surface of a p-doped substrate (204). The NPN structure (300) has a first n-doped region (242) coupled to an output terminal (106), a p-doped region (232, 243, 245) surrounding the first n-doped region (242) and coupled to the output terminal (107), and a second n-doped region (244) separated from the first n-doped region (242) by the p-doped region (243). The interface device (300) also includes a PNP structure (230) along a vertical depth of the p-doped substrate (204). The PNP structure (230) includes the p-doped region (243), an n-doped layer (234) under the p-doped region (243), and the p-doped substrate (204). Advantageously, the interface device (300) can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.
摘要翻译：在所描述的示例中，界面装置（300）包括沿着p掺杂衬底（204）的水平表面的NPN结构（Q1）。 NPN结构（300）具有耦合到输出端（106）的第一n掺杂区（242），围绕第一n掺杂区（242）的p掺杂区（232,243,245），并耦合到输出端（107）以及通过p掺杂区（243）与第一n掺杂区（242）隔开的第二n掺杂区（244）。界面装置（300）还包括沿着p掺杂衬底（204）的垂直深度的PNP结构（230）。 PNP结构（230）包括p掺杂区域（243），p掺杂区域（243）下方的n掺杂层（234）以及p掺杂衬底（204）。有利的是，接口设备（300）可以承受高电压摆动（正向和负向），防止下沉并获得大的负载电流，并且避免在断电操作期间进入低电阻模式。

2. 发明申请

WO2017151827A8 OUTPUT DRIVE WITH POWER DOWN PROTECTION 审中-公开
公开(公告)号：WO2017151827A8
公开(公告)日：2017-09-08
申请号：PCT/US2017/020294
申请日：2017-03-01
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： WU, Xiaoju , KELOTH, Rajesh , PRASAD, Sudheer
IPC分类号： H01L29/94 , H01L29/772 , H01L21/8224 , H02H7/09
摘要： In described examples, an interface device (300) includes an NPN structure (Ql) along a horizontal surface of a p-doped substrate (204). The NPN structure (300) has a first n-doped region (242) coupled to an output terminal (106), a p-doped region (232, 243, 245) surrounding the first n-doped region (242) and coupled to the output terminal (107), and a second n-doped region (244) separated from the first n-doped region (242) by the p-doped region (243). The interface device (300) also includes a PNP structure (230) along a vertical depth of the p-doped substrate (204). The PNP structure (230) includes the p-doped region (243), an n-doped layer (234) under the p-doped region (243), and the p-doped substrate (204). Advantageously, the interface device (300) can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.

3. 发明申请

WO2017152191A1 MOSFET TRANSISTORS WITH ROBUST SUBTHRESHOLD OPERATIONS 审中-公开
标题翻译：具有稳健的亚阈值操作的MOSFET晶体管
公开(公告)号：WO2017152191A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/021015
申请日：2017-03-06
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： WU, Xiaoju , THOMPSON, C., Matthew
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823814 , H01L29/0638 , H01L29/0847 , H01L29/1033 , H01L29/4238 , H01L29/78
摘要： In described examples of an integrated circuit with transistor regions (106) formed on a substrate, each transistor region (106) includes a channel region (116) and a terminal region (112, 114). The channel region (116) is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region (112, 114) is positioned adjacent to the channel region (116), and it is doped with a first dopant of a first conductivity type. Each transistor region (106) may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region (116) doped with a dopant and having a first doping concentration. Each transistor region (106) may include an edge recovery region (218) overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.
摘要翻译：在所描述的具有在衬底上形成的晶体管区域（106）的集成电路的示例中，每个晶体管区域（106）包括沟道区域（116）和端子区域（112,114）。沟道区域（116）沿横向尺寸定位，并且其包括沿着纵向尺寸的沟道边缘区域。端区（112,114）位于沟道区（116）附近，并且掺杂有第一导电类型的第一掺杂剂。每个晶体管区域（106）可以包括沿着纵向尺寸并且与沟道边缘区域相邻的边缘块区域。边缘块区域掺杂有与第一导电类型相反的第二导电类型的第二掺杂剂。掺杂有掺杂剂且具有第一掺杂浓度的沟道区（116）。每个晶体管区域（106）可以包括与沟道边缘区域重叠并且具有比第一掺杂浓度高的第二掺杂浓度的边缘恢复区域（218）。

4. 发明申请

WO2014071294A1 ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION 审中-公开
标题翻译：具有隔离SCR的ESD保护电路用于负压运行
公开(公告)号：WO2014071294A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/068276
申请日：2013-11-04
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： SALMAN, Akram, A. , FARBIZ, Farzan , CHATTERJEE, Amitava , WU, Xiaoju
IPC分类号： H01L29/66 , H02H9/00
CPC分类号： H01L27/0262 , H01L29/1012 , H01L29/7424 , H01L29/7436
摘要： A semiconductor controlled rectifier for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.
摘要翻译：公开了一种用于集成电路的半导体可控整流器。半导体可控整流器包括具有第一导电类型（N）的第一轻掺杂区域（100）和在第一轻掺杂区域内形成的具有第二导电类型（P）的第一重掺杂区域（108）。具有第二导电类型的第二轻掺杂区域（104）形成在第一轻掺杂区域附近。在第二轻掺杂区域内形成具有第一导电类型的第二重掺杂区域（114）。具有第一导电类型的掩埋层（101）形成在第二轻掺杂区域的下方并且电连接到第一轻掺杂区域。在第二轻掺杂区域和第三重掺杂区域之间形成具有第二导电类型的第三轻掺杂区域（102）。具有第二导电类型的第四轻掺杂区域（400）形成在第二轻掺杂区域和第三重掺杂区域之间，并且电连接到第二和第三轻掺杂区域。

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